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% Rick Ridell
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\newcommand{\Oct}{{\sc Oct}}
\newcommand{\unix}{{\sc unix}}
\newcommand{\bdsyn}{{\sc bdsyn}}
\newcommand{\espresso}{{\sc espresso}}
\newcommand{\IF}{{\sc if}}
\newcommand{\LEAVE}{{\sc leave}}
\newcommand{\RETURN}{{\sc return}}
\newcommand{\ROUTINE}{{\sc routine}}
\newcommand{\SELECT}{{\sc select}}
\newcommand{\SELECTONE}{{\sc selectone}}
\newcommand{\SELECTALL}{{\sc selectall}}
\newcommand{\FOR}{{\sc for}}
\newcommand{\THEN}{{\sc then}}
\newcommand{\ELSE}{{\sc else}}
\newcommand{\MIS}{{\sc mis}}
\newcommand{\BLIF}{{\sc blif}}
\newcommand{\yacc}{{\sc yacc}}
\newcommand{\meta}{meta-variable}
\newcommand{\Meta}{Meta-variable}
\newcommand{\BDS}{{\sc bds}}
\newcommand{\DECSIM}{{\sc decsim}}
\newcommand{\PLA}{{\sc pla}}
\newcommand{\PLAs}{{\sc pla}'s}
\newcommand{\DC}{{\tt DONT\_CARE}}
\newcommand{\MOS}{{\sc mos}}
\newcommand{\Vdd}{{\sc V}dd}
\newcommand{\GND}{{\sc GND}}
\newcommand{\FIFO}{{\sc fifo}}

\newenvironment{code}%
{%
	\begin{pespace}\nopagebreak[3]\begin{verbatim}%
}%
{%
	\end{pespace}%
}%

\title{
	Berkeley Logic Interchange Format (\BLIF )
}

\author{
	University of California\\
	Berkeley
}

\begin{document}

\maketitle

The goal of \BLIF\ is to describe a Boolean network in textual form.
A Boolean network is a representation of an arbitrary
combinational logic network, and is an acyclic directed graph with
a logic function attached to each node.
Each node in this representation has a single output.
Therefore, each net (or signal) has only a single driver, and we can
therefore name either the signal or the gate which drives the
signal without ambiguity.

In this section, angle-brackets surround
nonterminals, and vertical bar separates choices in a pseudo-BNF style.
Bdsyn uses only the {\em logic-gate} construct of \BLIF .
Bdsyn uses the the keywords {\em .module, .inputs, .outputs, .end,}
and {\em .names}.
The {\em module-reference} construct of \BLIF\ is not implemented.

\section{Modules}
A module is declared by:

\begin{code}
    .module <decl-module-name>
    .inputs <decl-input-list>
    .outputs <decl-output-list>
    <logic-gate> | <pla-reference> | <module-reference> | <timing-constraints>
             .
             .
             .
    <logic-gate> | <pla-reference> | <module-reference> | <timing-constraints>
    .end
\end{verbatim}\end{code}

{\em decl-module-name} is a string giving the name of the module.

{\em decl-input-list} is a white-space-separated list of strings
(terminated by the
end of the line) giving the formal parameters for the module being
declared.  If this is the last or only module, then these signals can be
identified as the primary inputs of the circuit.
Multiple {\em .inputs}
lines are allowed, and the lists of inputs are merely concatenated.

{\em decl-output-list} is a white-space-separated list of strings
(terminated by the
end of the line) giving the formal parameters for the module being
declared.  If this is the last or only module, then these signals can be
identified as the primary outputs of the circuit.
Multiple {\em .outputs}
lines are allowed, and the lists of inputs are merely concatenated.

It is expected that a \BLIF\ parser may allow the
{\em .inputs} and {\em .outputs} statements to be optional.
If they are not specified, the primary inputs can be 
inferred from the signals which
are not the outputs of any other logic block, and the primary outputs can be
inferred from the signals which are not the inputs to any other
blocks.  This makes the serious assumption that no primary
output is used as an intermediate signal.
Also, these assumptions are only useful for the ``root'' module.
Subcircuits are invoked with positional arguments and hence the
specified order for the inputs is significant in a subcircuit.

The keyword {\em .end} is optional, and is implied at the end of the file.

Anywhere in the file, a `\verb|\|' (backslash) as the last character on a
line indicates concatenation of the subsequent line to the current line.
\section{Logic Gates}
A {\em logic-gate} is:

\begin{code}
    .names <in-1> <in-2> ... <in-n> <output>
    <single-output-cover>
\end{verbatim}\end{code}

{\em single-output-cover} is an n-input, 1-output PLA description of the logic
function corresponding to the logic gate.  \{0, 1, --\} is used in the
``input plane'' and \{0, 1, --, \verb|~|\} is used in the ``output plane''.
The logic gate can have only its ON-set specified with 1's in the
``output plane'', or can also have a DC-set and an OFF-set specified
with -'s or 0's in the ``output plane''. \verb|~| means no connection.
For a more
complete description of the PLA input format, see {\em espresso(5)}.

\section{Module (subcircuit) references}
A {\em module-reference} is

\begin{code}
    .subckt <module-name> <input-list> <output-list>
\end{verbatim}\end{code}

{\em module-name} gives the name of a module being included.  It must be
previously defined in the file.
{\em input-list} are the actual parameters and are
matched one-to-one with the
corresponding {\em decl-input-list} inside the module declaration.
Likewise, {\em output-list} are the actual parameters and are
matched one-to-one with the
corresponding {\em decl-output-list} inside the module declaration.

{\em input-list} and {\em output-list} are white-space separated sequence
of tokens ending with the end of the line.
A ``/'' may be used to separate {\em input-list} from {\em output-list}.
The end of {\em input-list} and the start of {\em output-list} is, however,
always inferred from the number of inputs and outputs in the module
declaration (i.e., from {\em decl-input-list} and {\em decl-output-list} of the
module which is being called).

If both {\em input-list} and {\em output-list} are not given, then the
formal parameters within the module declaration become the actual
parameters.  It is an error if the {\em input-list} and {\em output-list}
are given and the number of inputs or outputs does not match the ``call''
and the definition.

\section{PLA References}

A {\em pla-reference} is
\begin{code}
    .pla <pla-name> <input-list> <output-list>
\end{verbatim}\end{code}

{\em pla-name} gives the name of a file
containing a \PLA\ description in the format understood by {\em espresso(5)}.
{\em input-list} and {\em output-list} are matched 1 for 1 with the inputs and
outputs of the PLA (which, for arcane reasons are given via .ilb and .ob
keywords within the PLA).  Similar to {\em .subckt}, a ``/'' may separate
the input-list and the output-list and if both are missing, the formal
parameters become the actual parameters.


\section{Timing Constraints}

A {\em timing-constraints} is one or more of 
\begin{code}
    .input_arrival <in-name> <rise> <fall>
    .output_required <out-name> <rise> <fall>
    .input_drive <in-name> <rise> <fall>
    .output_load <out-name> <load>
    .default_input_arrival <rise> <fall> 
    .default_output_required <rise> <fall>
    .default_input_drive <rise> <fall>
    .default_output_load <load>
\end{verbatim}\end{code}

{\em rise}, {\em fall}, {\em drive}, and {\em load} are all floating point
numbers giving the rise time, fall time, input drive, and output load.
{\em input\_arrival} sets the input arrival time for the input {\em in-name}.
{\em output\_required} sets the output required time for the output 
{\em out-name}.
{\em input\_drive} sets the input drive for the input {\em in-name}.
{\em input\_load} sets the output load for the output {\em out-name}.
{\em defualt\_input\_arrival, default\_output\_required, default\_input\_drive,
defualt\_output\_load} set the corresponding default values for all the
inputs/outputs whose values are not specifically set.
There is no unit for all the timing and loading numbers.
Special attention should be given when specifying and interpreting the values.
\end{document}
