// add traces for some signals (after deleting the existing traces) delete traces CLK RESET In1 In2 Out add traces CLK RESET In1 In2 Out //create a 100MHz symmetric clock set Clock period 10 force CLK 1 0 -repeat force CLK 0 5 -repeat // apply an initial reset pulse force RESET 1 0 -fixed force RESET 0 50 -fixed // force inputs to desired values force In1 0 0 -fixed force In2 0 0 -fixed force In1 1 100 -fixed force In2 1 100 -fixed force In1 0 200 -fixed force In2 0 300 -fixed // run the simulation for 1000ns run 1000