CS/ECE 755: Discussion Session I

  • The Overall Picture,

  • Some Layout Examples,

  • Standard-Cells Methodology.

    • by

    Constantinos Dovrolis

    dovrolis@cs.wisc.edu

    Monday, February 15 1999.

    The Overall Picture

    The objective in this course is to cover the entire design process, starting from the architecture of a system down to the physically verified VLSI layout. The toolset consists of about ten Mentor Design tools that are briefly covered with on-line Tutorials.

    Some Layout Examples

    A CMOS inverter

    A 3-input NOR gate

    What is the following?

    Standard Cells Methodology

    A few words about the scn08hp library of standard cells:

  • ANDs and ORs with 2,3,4 inputs,
  • NANDs and NORs with 2,3,4 inputs (with or without buffered output),
  • Buffers and Tri-State Buffers (three sizes),
  • 2-input mux
  • D-latch (set, reset)
  • D-flip-flop (set, reset)
  • XOR, XNOR (2-inputs)
  • AO-112 to -444
  • AOI-112 to -444
  • OA-112 to -444
  • OAI-112 to -444

    • Suppose that we want to design an 8-bit 2-by-1 multiplexer, using the following 2-by-1 multiplexer

    The 8-bit multiplexer logic design

    After floorplanning

    After placement

    After routing (first design)

    After routing (second design)

    After routing (third design)

    After Layout-Versus-Schematic (LVS) checks

    Quicksim simulation with backannotated layout information

    The END...