CS/ECE 755: Discussion Session II

  • More on Cell and Port Placement,

  • More on Routing,

  • More on Backannotation.

  • Circuit Simulations with Accusim.
  • by

    Constantinos Dovrolis


    Monday, February 22 1999.


    Already covered:

  • Logic Design using the SCN08HP Library (Tutorial-2)

  • Digital Simulations with Timing Information using QuickSim (Tutorial-2)

  • Automatic Generation of Standard-Cells Layout using IC Station (Tutorial-4)

  • Full-Custom Layout Editing using IC Station (Tutorial-3)

  • DRC and LVS Layout verification (Tutorials 3 and 4)

  • Backannotation of QuickSim Simulations with Layout Parasitics (Tutorial-4)

    To be covered:

  • Extraction of Netlist from Layout with Lumped and Distributed Parasitic Models, and Simulation with Accusim (Tutorial-5)

  • Schematic-Driven-Layout (Tutorial-6)

  • Hierarchical Placement and Routing of Layout Blocks (Tutorial-7)

  • Depending on time and project needs: Advanced features of IC Station, QuickPath, VHDL Synthesis using the SCN08HP library

  • More on Cell and Port Placement

    From the IC Station Reference Manual: (run mgc_acroread)

    Cell Placement (see textbook, section


    Initial and Improve:

    Random and Improve:


    Port Placement:

    More on Routing

  • Channel Router
  • Over-the-Cell-Router (OCR)

    Routing Steps:

    Routing Options:

  • Initial and Improve Global Iterations:

    Number of iterations for global routing. The router minimizes the layout area by rerouting nets in congested areas.

  • Feedthru Cost:

    The OCR router can either insert an external feedthru between cells, or an internal feedthru over the cell. A lower cost makes external feedthru more likely.

  • Primary Routing Layer:

    When it is based on the channel direction, Metal-2 is used for vertical channels and Metal-1 for horizontal channels.

  • Extra Tracks:

    Number of extra track spaces to leave in each channel. This space can be used for manual editing.

  • Expand Channels:

    Specify whether router is allowed to change size of channel areas.

    Expert Routing Options:

  • Channel Over Cell Routing:

    Specify whether any routing space inside a cell should be used for channel routing.

  • Capacity-Driven-Layout:

    Specify whether the routing decisions should be based on minimizing the capacitance of interconnections.

  • Taper Power:

    Specify whether the VDD/GND lines should be `tapered' during routing.

  • Connect Block Power:

    Specify whether VDD/GND connections should be made on all blocks.

  • Create Power Grid:

    Specify whether a grid of VDD/GDD lines should be created in all channels (when routing blocks).

  • Align Mode:

    Specify alignment of layout blocks when routing is done.

    Over-the-Cell-Routing (OCR) Options:

  • Routing Levels:

    The routing layers that will be used. The first layer specified is the least preferred.

  • Operation Mode Type:

    Specify whether routing should be done near the edges or the center of the channels.

  • Restricted Levels:

    It is possible to specify the Poly layer here, for initial route segments directly from the gate of transistors.

  • Work Factor:

    Determines the number of iterations of the algorithm.

  • Maximum number of Bends and Vias:

    The bends refer to the same routing layer, while the vias refer to adjacent routing layers.

  • More on Backannotation

    Backannotation VS Netlist Extraction:

    Circuit Simulations with Accusim

    A transmission-gate-based 2-input XOR gate with 6 transistors:

    Transient Analysis Setup:

    Pulse and PWL Force Specifications:

    Simulation Traces:

    The END...