CS/ECE 755: Discussion Session IV

  • Schematic-Driven-Layout

  • More on Layout-Versus-Schematic (LVS) verification

  • More on Assignment - Phase II

  • Discussion about possible projects
  • by

    Constantinos Dovrolis

    dovrolis@cs.wisc.edu

    Monday, March 15 1999.


    Agenda for today:

  • Phase II of Assignment

  • More on LVS (for transistor-based schematics)

  • Schematic-Driven-Layout

  • Discuss Phase III of assignment and possible projects

  • More on LVS

    Associate full-custom layout with transistor schematic: (use Connectivity-Editing and SDL viewpoint)

    Do not identify gates, but devices.

    For now, ignore the errors on missing "bulk" pins.


    Schematic-Driven-Layout

    See Tutorial-7.


    IC Station Objects


    The END...