"A 2.6-GBytes/s Multipurpose Chip-to-Chip Interface", B.Lau et.al. (Rambus)

See

IEEE Journal of Solid-State Circuits, November 1998

RSL Data Channel network

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System Configurations: Chip-to-Chip, Chip-to-DRAM

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Three-stage Input Receiver

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Internal Clock Jitter Plot

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Clock Distribution

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Slew-Rate Control Circuit

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Slew-Rate Detector

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Channel Equivalent Circuit

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Channel Frequency Response

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Data and Clock Waveform at 1.3Gbps/pin

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Channel Data Eye Diagram

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Transmit Shmoo Plot

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