CS/ECE 755-1, Spring 2002

Homework 2

due Monday February 25, in class

Approximate weight: 3%

Problem 1: (10 points)

Draw the layout (using colored pencils) for a 3 input AND gate implemented in Domino logic. Use graph paper, and draw to scale (e.g., one square on the paper is one square lambda). Be sure to respect the SCMOS design rules.

Problem 2: (10 points)

Draw a sticks diagram showing the layout for the following function: Implement a static CMOS (complementary) gate. Remember that sticks diagrams should not show dimensions, but should respect layers (i.e., two metal 1 layers cannot cross each other). Use metal 1 only within the cell, except where inputs and outputs should connect to the cell.

Problem 3: (30 points)

You are to design and optimize a non-inverting buffer to drive a large 2 pf load. Your goal is to minimize the delay subject to acceptable noise margins. You should design the device using DA and simulate using Accusim. Use the method we discussed in class to calculate your noise margins. For the first two parts, assume that "acceptable noise margin" means at least 10% of Vdd.

The first stage of the buffer should be a "minimum" size inverter with a 10 lambda wide PMOS device and a 5 lambda wide NMOS device. The output load should be 2 pf. You may use as many stages in your buffer as you like, and you may size the transistors as you like.

  1. Optimize the design so that the rise and fall times of the output are approximately equal. What is the overall delay? What are your noise margins?
  2. For some circuits, one edge is more important than the other. Re-optimize your design to minimize the rise time on your buffer's output. The fall time can be as slow as you like. What is the rise time? What is the fall time? How large are your noise margins (they should not be less than 10% of Vdd)?
  3. Many designers feel that 20% of Vdd is the minimum acceptable noise margin. Would using this larger noise margin impact your design? If so, how fast would your device be with these larger margins?