Automatic Placement and Routing of Hierarchical Layout Blocks.
Constantinos Dovrolis
University of Wisconsin, Madison
Spring 1999.
You already know how to create layout blocks for relatively small designs, using full-custom drawing, SDL, or standard cells. For large designs, however, it is likely that the final layout will consist of several pre-designed layout blocks, that make up hierarchically the overall physical layout of the design. In this tutorial you will learn how to use the automatic placement and routing tools of IC Station for such multi-block designs.
Suppose that you have designed a hierarchical datapath circuit, such as the following:
The schematics for the individual components of this design are:
In this example, all the blocks are made up of standard cells, except the XOR gates which are created using SDL. The important point here is the properties that you see attached to each logic symbol. These are the properties COMP (for Component) and PHY_COMP (for Physical Component). What these properties do is that they associate a logic symbol with a layout block that you have already created for that logic symbol. The property COMP is the name of the layout cell (as created in IC Station), while the property PHY_COMP is the path for that layout block. For example, the values of these properties for the 6-bit Wallace multiplier are:
You can add these properties in Design Architect selecting the appropriate symbol, and then selecting the menu Properties -> Add ->Add Multiple Properties.
The layout for the above components of the hierarchical design are:
Note that in this example it is only the 8-bit 2-input XOR blocks that consist of hierarchical layout themselves. Also, any of these components could be full-custom layout blocks, instead of standard-cell, or SDL blocks.
Suppose that you have already designed the top-level logic design, the individual layout blocks, and that you have added the properties COMP and PHY_COMP for the correspondence between logic symbols and layout blocks. Also, note that for the SDL and full-custom logic symbols, you need to connect externally the VDD and GND pins to the appropriate power supplies. At this point you can create the hierarchical layout in IC Station, using the automatic placement and routing tools. First, though, you need to create a design viewpoint for the top-level schematic using DVE. The creation of this viewpoint follows the same steps as the creation of a viewpoint for IC Trace, i.e., just create a viewpoint for the top-level schematic, and add a primitive called element.
Now, in IC Station create a cell for the top-level design with the follows settings:
Note that you have to specify the library of standard cells, even if your top-level design does not include individual standard cells. The reason is that that library includes some special layout components, such as "corners", "feedthrus", and "vias". Also, note that the Editing Mode has to be Connectivity Editing, and that the Logic Loading has to be User Defined.
Next, you can place the layout blocks, using the Autoplace Blocks function of the Place & Route menu. The menu that will appear is:
For the explanation of these parameters, see the related pages from the IC Station Reference Manual:
After you place the blocks, select View All. Then, place the ports as you already know how to do, and then select Autoroute All for the automatic routing of the interconnections between the layout blocks. For the previous example, this is one version of the final layout:
In large hierarchical layout blocks, we often have to deal with overflows, i.e., with interconnections that IC Station did not manage to route. Overflows are shown as yellow lines, connecting the points that have not been connected.
There is a large number of things you can do in case of overflows. If the number of overflows is large, you can select to place the blocks again, using a larger value for "partition area" or for the "white space" parameters. The placement of ports is also often critical in the routing success. Another approach is to try to route again, but this time with an increased value for the "work effort" parameter of the router (see the options of the AutoRoute function). Finally, you can just try to route the overflow manually, using the AutoRoute -> Point-to-Point function, in which you can create an interconnection for the overflow using any path you want.
It is important to verify that the produced layout corresponds correctly to the underlying logic diagram. Since you should have already checked at this point the individual layout blocks, both using DRC and LVS, the purpose of running LVS now is to verify the connectivity between layout blocks in the top-level layout block. In order to do so, run IC Trace(D) (which stands for Direct Mode), as opposed to IC Trace(M) (which stands for Mask Mode). IC Trace(M) would try to "look into" the layout blocks and verify the connectivity internally in each of them, while IC Trace(D) will only check the top-level connectivity between blocks.
When you run LVS, select the viewpoint that you created for IC Trace, and as done usually, specify that GND is also a ground name. Also, remove the type property "phy_comp" from the type properties in the LVS Setup menu, as shown next:
Before performing DRC with IC-rules in any block that uses the scn08hp library of standard cells, we have to remove the select overlap design rule, and the design rule 8.4, because this library of standard cells violates these rules. This can be done with the Select -> Rules Menu in IC Rules, as shown:
Another problem with the configuration of IC Station is that the Metal-1 paths that connect to the ports of layout blocks do not extend to the block boundary, but they are one lambda shorter (..), as shown next.
This can cause design rule violations in the top-level layout, and so we have to manually extend the Metal-1 paths that connect to the ports of a layout block by one lambda, as shown next.
You can do so extending the path's centerline, so that the path reaches the cell's vertical boundary. This needs to be done only for the Metal-1 port paths (which are only the horizontal port paths). We do not have the same problem with the Metal-2 port paths.
Note finally that it is better to do this (tedious) modification in the individual layout blocks once, after you have finalized their design and verification.
