Hierarchial design using IC station


   This tutorial guides you through the process of creating hierarchial designs. In this tutorial we will make the layout of two inverters in series. In order to proceed with this tutorial you should have laid out a inverter in IC station. Also, you should have created a schematic with both your inverters in Design architect and should have run the adk_dve on the schematic.
 

1) Create a sheet in IC station as you did for the basic inverter cell (Steps 1 - 5 in tutorial 1). Be sure to select logic loading options->Flat in the Create Cell dialog box.

2) Select Objects->Add->Cell. Enter the full path to the cell in the dialog box that appears and then place the cell. Your sheet will look similar to the one shown in Figure 1.
 
 

Figure 1

3) In order to view the cell, select peek on view in the Setup->IC dialog box.

4) Following step2 add another cell as shown in Figure 2.
 
 

Figure 2

5) As per the schematic we have substrates of both the nfets at the same potential (GND) and that of the pfets at the same potential (VDD). Hence we can "abut" the cells as shown in Figure 3. We can do this even in the basic cells. You should not do this between a nmos and a pmos.
 
 

Figure 3

6) Next step would be to make the necessary connections between the two cells. A point to note in Figure 3 is that there is no need to make explicit connections between the OUT of the first inverter and IN of the second inverter or between the power lines of the two cells. This is because the layout of the basic cell and the hierarchy has been planned such that the lines to be connected touch or overlap when the cells are abutted. This will make your layout look neat.

7)  Ports at this level need to be placed. In this case we need the following ports: IN, OUT, VDD, GND. After placing the ports the final layout will look like the one in Figure 4. You can place ports on the ports belonging to lower level cells as in case of IN port in the figure (you can distinguish between the two by just looking at them).
 
 

Figure 4

8) To distinguish between ports of the current hierarchy and the lower ones, select the port. If the port you selected belongs to this hierarchy, you will get a message on the status bar similar to the one in Figure 5. This message was displayed when the OUT port of the current context was selected. If you select a port of a lower level cell you will get a message similar to the one in Figure 6. This message was displayed on selecting IN port of one of the inverter instances.
 
 

Figure 5


 
 

Figure 6

9) All this while your current working context was the topmost level. You can set your contexts to cells at lower levels. In our case we can edit the basic inverter cell by choosing Context->hierarchy->Set context and either click on the desired cell or enter the full path to the cell in the dialog box that appears.

      NOTE: Any change made to the cells in the lower context will change permenantly change that cell when saved. Hence the change made will reflect in every instance   of that cell at all hierarchies in the current layout and even in other layouts.

10) To move higher in the hierarchy, choose Context->hierarchy->set context up and enter the number of levels.

11) While saving the layout you can specify whether to save the current context or the entire hierarchy by using File->Cell->Save cell menu.