headquarters henderson nevada united states products active hdl alint riviera pro spec tracer hes dvm hes 7 website aldec.com aldec inc. is a privately owned electronic design automation company and provides software and hardware used in creation and verification of digital designs targeting fpga and asic technologies . headquartered in henderson nevada aldec also has offices development centers in europe uk japan israel india china taiwan poland and ukraine . as a member of accellera and ieee standards association aldec actively participates in the process of developing new standards and updating existing standards e.g. vhdl systemverilog . aldec provides hdl simulation engine for other eda tools e.g. altium designer 1 and bundles special version of its tools with fpga vendors software e.g. lattice 2 . contents 1 history 2 products 2.1 software 2.2 hardware 3 education 4 see also 5 references 6 external links history edit aldec was founded in 1984 by dr. stanley m. hyduke . in 1985 the company released its first product ms dos based gate level simulator susie . for the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as orcad . sensing growing popularity of microsoft windows aldec ported its simulator to this platform and added schematic entry and design management tool . the new software suite was released in 1992 as active cad some low end versions of the suite were for some time sold under susie cad brand . one of the distinguishing features of active cad was the ability of instantaneous transfer of schematic changes to the simulator allowing quick verification of the behavior of the modified circuit . in 1996 aldec signed agreement with xilinx that allowed distribution of xilinx only version of active cad under the foundation name . while vhdl and verilog were supported by active cad in the form of schematic macros the release of active vhdl in 1997 marked the shift from netlist based design to hdl based design . after adding verilog support active vhdl was renamed to active hdl and is still available as of 2007 . in 2000 aldec released high performance hdl simulator working not only on windows but also on solaris and linux platforms . 3 in 2001 aldec added hardware to its product line hes hardware embedded simulation platform that allows hardware acceleration of hdl simulation and incremental prototyping of hardware . year 2003 marks the release of riviera pro supporting assertion based verification openvera psl and systemverilog can be used to write properties assertions and coverage . support for systemc and non assertion part of systemverilog was added in 2004 . interfaces to matlab and simulink appeared in aldec tools for the first time in 2005 . in 2006 riviera pro was the first simulator supporting open ip encryption initiative by synplicity . 4 stimulated by requests from verilog users aldec released in 2007 an advanced user configurable lint tool implementing rules created by starc japanese consortium of major silicon vendors . in 2008 releases alint design rule checker starc japanese consortium of 11 asic companies 2010 releases support for vhdl ieee 1076 2008 . in 2010 aldec s active hdl wins best fpga design & simulation tool in china in 2011 aldec delivers uvm 1.0 ovm 2.1.2 & vmm 1.1.1 a support releases 4 mhz design emulator and wins best fpga design & verification platform provider in china . in 2012 aldec enters soc asic prototyping market with hes 7 and jointly launches osvvm vhdl verification . in 2013 aldec releases spec tracer requirements lifecycle management in 2014 aldec celebrates 30 years in eda . in 2015 aldec releases alint pro cdc for cdc verification . products edit software edit active hdl fpga development environment built around common kernel hdl simulator . supports text based and graphical design entry and debugging tools allows mixed language simulation vhdl verilog edif systemc systemverilog and provides unified interface to various synthesis and implementation tools . also supports assertion based verification with open vera psl or systemverilog assertion statements . special versions of the software that support just one fpga vendor are available e.g. active hdl lattice edition . only available on ms windows platform . riviera pro high end hdl simulator targeting asic and large fpga designs . riviera pro extends active hdl s simulation features with support for advanced verification methodologies such as linting functional coverage ovm and uvm hardware acceleration and prototyping . riviera pro is a new generation of the tool known as riviera classic and is available in 32 bit and 64 bit on ms windows and linux . hes dvm solution allowing acceleration of hdl simulation 10x to 50x verification time reduction emulation of the entire design and hardware software co simulation useful in embedded system development . alint dedicated design rule checker linting tool . alint is able to conduct extensive textual analysis of individual verilog and vhdl sources and advanced checks of the entire design hierarchy . multiple sets of highly configurable predefined rules are available and new custom rules can be created using provided api . built in phase based linting methodology allows faster more efficient checking of rules . spec tracer unified requirements life cycle management application designed specifically for fpga and asic designs . facilitates requirements capture management analysis traceability and reporting ; integrates with windows based hdl design and simulation tools . ip products a set of general purpose intellectual property blocks created by aldec and its partners validated in active hdl and riviera pro environments . hardware edit hes 7 high capacity high density fpga based asic prototyping solution . with help of xilinx virtex 7 fpga based prototyping boards hes 7 allows testing designs of up to 24 million asic gates . microsemi rtax rtsx prototyping the efficient way of prototyping designs with radiation hardened fpga by using footprint compatible prototyping boards with flash based reprogrammable chips on top . the solution includes optional software for netlist translation . do 254 compliance tool set cts it is a complete verification solution that can assure the fpga on your system to be do 254 ed80 compliant . the cts gives the user the ability to perform an advanced way of in hardware simulation instead of the traditional hardware testing . as test vectors for the in hardware simulation you can reuse the same testbench with 100 % code coverage results captured from rtl simulation . by reusing the same testbench the hardware verification can easily achieve requirements traceability . you can perform the in hardware simulation at speed at the target device . the cts also allows easy comparison and debugging of the in hardware simulation and hdl simulation results via waveform format . education edit aldec provides fully functional heavily discounted versions of its software for educational institutions worldwide kumaon engineering college national technology university . aldec also offers a special student edition of active hdl downloadable from aldec s website . the student edition has limited design capacity and some reduction of program functionality but supports both design languages verilog vhdl . the company also supports local education in 1999 it contributed to the establishment of the aldec digital design laboratory at the unlv . 5 aldec software is packaged with several electronic design related books e.g. digital design principles and practices contemporary logic design . student edition of active hdl was the first hdl simulator to be sold at walmart . 6 see also edit vhdl verilog references edit eetimes news aldec fpga simulation added to altium designer eetimes.com 2010 5 25 en genius programmable logic zone lattice and aldec form alliance for fpga design and design verification richard goering aldec rolls out linux based mixed language simulator eetimes.com november 13 2000 christine evans pughe protecting your ip just got simpler paragraph 11 electronics weekly october 13 2006 ece unlv staff aldec ... plays a significant role in ece programs page 3 ece unlv news vol 5 2005 edn online staff eda software sold in walmart . edn february 20 2006 external links edit official site v t e programmable logic concepts asic soc fpga logic block cpld epld pla pal gal reconfigurable computing xputer soft microprocessor circuit underutilization languages verilog a ams vhdl ams vital systemverilog dpi systemc ahdl handel c psl upf palasm abel cupl openvera c to hdl flow to hdl myhdl jhdl ella companies accellera actel achronix amd aldec altera atmel cadence cypress duolog forte intel lattice national mentor graphics microsemi signetics synopsys magma virage logic texas instruments tabula xilinx products hardware ice stratix virtex software altera quartus xilinx ise xilinx vivado modelsim vtr simulators ip proprietary arc leon latticemico8 microblaze picoblaze nios nios ii open source latticemico32 opencores openrisc 1200 risc v jop retrieved from https en.wikipedia.org w index.php title aldec & oldid 692375317 categories electronic design automation companieselectronics companies of the united statescompanies established in 1984companies based in henderson nevada navigation menu personal tools not logged intalkcontributionscreate accountlog in namespaces article talk variants views read edit view history more search navigation main pagecontentsfeatured contentcurrent eventsrandom articledonate to wikipediawikipedia store interaction helpabout wikipediacommunity portalrecent changescontact page tools what links hererelated changesupload filespecial pagespermanent linkpage informationwikidata itemcite this page print export create a bookdownload as pdfprintable version languages edit links this page was last modified on 25 november 2015 at 06 58 . text is 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