founder andreas olofsson headquarters lexington massachusetts us key people andreas olofsson ceo products central processing units owner privately funded website adapteva.com adapteva is a fabless semiconductor company focusing on low power many core microprocessor design . the company was the second company to announce a design with 1 000 specialized processing cores on a single integrated circuit . 1 2 adapteva was founded in 2008 with the goal of bringing a ten times advancement in floating point performance per watt for the mobile device market . products are based on its epiphany multi core mimd architecture and its parallella kickstarter project promoting a supercomputer for everyone in september 2012 . the company name is a combination of adapt and the hebrew word teva meaning nature . contents 1 history 2 products 2.1 scalability 2.2 multi core coprocessors 2.3 parallella project 2.4 performance 3 see also 4 references 5 further reading 6 external links history edit adapteva was founded in march 2008 by andreas olofsson . the company was founded with the goal of bringing a 10 advancement in floating point processing energy efficiency for the mobile device market . in may 2009 olofsson had a prototype of a new type of massively parallel multi core computer architecture . the initial prototype was implemented in 65 nm and had 16 independent microprocessor cores . the initial prototypes enabled adapteva to secure us 1.5 million in series a funding from bittware a company from concord new hampshire in october 2009 . 3 adapteva s first commercial chip product started sampling to customers in early may 2011 and they soon thereafter announced the capability to put up to 4 096 cores on a single chip . the epiphany iii was announced in october 2011 using 28 nm and 65 nm manufacturing processes . products edit adapteva s main product family is the epiphany scalable multi core mimd architecture . the epiphany architecture could accommodate chips with up to 4 096 risc out of order microprocessors all sharing a single 32 bit flat memory space . each risc processor in the epiphany architecture is superscalar with 64 32 bit unified register file integer or single precision microprocessor operating up to 1 ghz and capable of 2 gflops single precision . epiphany s risc processors use a custom instruction set architecture isa optimised for single precision floating point 4 but are programmable in high level ansi c using a standard gnu gcc tool chain . each risc processor in current implementations ; not fixed in the architecture has 32 kb of local memory . code possibly duplicated in each core and stack space should be in that local memory ; in addition most temporary data should fit there for full speed . data can also be used from other processor cores local memory at a speed penalty or off chip ram with much larger speed penalty . the memory architecture is does not employ explicit hierarchy of hardware caches similar to the sony toshiba ibm cell processor but with the additional benefit of off chip and inter core loads andstores being supported which simplifies porting software to the architecture . it is a hardware implementation of partitioned global address space . citation needed this eliminated the need for complex cache coherency hardware which places a practical limit on the number of cores in a traditional multicore system . the design allows the programmer to leverage greater foreknowledge of independent data access patterns to avoid the runtime cost of figuring this out . all processor nodes are connected through a network on chip allowing efficient message passing . 5 scalability edit the architecture is designed to scale almost indefinitely with 4 e links allowing multiple chips to be combined in a grid topology allowing for systems with thousands of cores . multi core coprocessors edit 16 core adapteva epiphany chip e16g301 from parallella single board computer on august 19 2012 adapteva posted some specifications and information about epiphany multi core coprocessors . 6 technical info for e16g301 7 e64g401 8 cores 16 64 core mhz 1000 800 core gflops s 2 1.6 sum ghz 16 51.2 sum gflops 32 102 mm 8.96 8.2 nm 65 28 w def . 0.9 1.4 w max . 2 2 in september 2012 a 16 core version the epiphany iii e16g301 was produced using 65 nm 9 11.5 mm2 500 mhz chip 10 and engineering samples of 64 core epiphany iv e64g401 were produced using 28 nm globalfoundries process 800 mhz . 11 the primary markets for the epiphany multi core architecture include smartphone applications such as real time facial recognition speech recognition translation and augmented reality . next generation supercomputers requiring drastically better energy efficiency to allow systems to scale to exaflop computing levels . floating point acceleration in embedded systems based on field programmable gate array architectures . parallella project edit parallella single board computer with 16 core epiphany chip and zynq 7010 fpga in september 2012 adapteva started project parallella on kickstarter which was marketed as a supercomputer for everyone . architecture reference manuals for the platform were published as part of the campaign to attract attention to the project . 12 the us 750 000 funding goal was reached in a month with a minimum contribution of us 99 entitling backers to obtain one device ; although the initial deadline was set for may 2013 the first single board computers with 16 core epiphany chip were finally shipped in december 2013 . 13 size of board is planned to be 86 mm 53 mm 3.4 in 2.1 in . 14 15 16 the kickstarter campaign raised us 898 921 . 17 18 raising us 3 million goal was unsuccessful so no 64 core version of parallella will be mass produced . 19 kickstarter users having donated more than us 750 will get parallella 64 variant with 64 core coprocessor made from initial prototype manufacturing with 50 chips yield per wafer . 20 parallella 16 micro server parallella 16 desktop computer parallella 16 embedded platform use case ethernet connected headless server a personal computer leading edge embedded systems processor dual core 32 bit arm cortex a9 with neon at 1 ghz part of zynq z7010 chip by xilinx dual core 32 bit arm cortex a9 with neon at 1 ghz part of zynq z7020 chip by xilinx coprocessor 16 core epiphany iii multi core accelerator e16 memory 1 gb ddr3l ram ethernet 10 100 1000 usb n a 2 usb 2.0 usb 2.0 hs and usb otg display n a hdmi storage 16 gb microsd expansion n a 2 elinks 24 gpio 2 elinks 24 gpio fpga 28k programmable logic cells 80 programmable dsp slices 80k programmable logic cells 220 programmable dsp slices weight 36 g 1.3 oz 38 g 1.3 oz size 3.5 mm 2.1 mm 0.625 mm 0.1378 in 0.0827 in 0.0246 in sku p1600 dk xx p1601 dk xx p1602 dk xx hts code 8471.41.0150 power usb powered 2.5 w or 5 v dc 5 w performance edit the neutrality of this section is disputed . relevant discussion may be found on the talk page . please do not remove this message until conditions to do so are met . june 2016 learn how and when to remove this template message joel hruska from extremetech has the following opinion about the parallella project adapteva is drastically overselling what the epiphany iv can actually deliver . 16 64 tiny cores with small amounts of memory no local caches and a relatively low clock speed can still be useful in certain workloads but contributors aren t buying a supercomputer they re buying the real world equivalent of a self sealing stem bolt . 21 the criticism that the epiphany chips can not provide anywhere near the performance of modern supercomputers is nevertheless correct actually epiphany chips with 16 cores or 64 cores and c. 25 or 100 gflops in single precision respectively do not even match the floating point performance of modern desktop pc processors core i7 4770k haswell 4 cores 3.5 ghz avx2 177 gflops 22 double precision a fact that is acknowledged by adapteva . however the latest parallella boards with e16 epiphany chips 23 can be compared to many ancient supercomputers in terms of raw performance just as an example the cray 1 the first supercomputer per se had a peak performance of 80 mflops at 1976 and its successor the cray 2 had a peak performance of 1.9 gflops at 1985 and can certainly be used for parallel code development ; the architectural similarities to supercomputers message passing and numa make it a potentially useful development system compared to traditional smp machines . the point being that for a power envelope of 5 w and in terms of gflops mm2 of chip die space the current e16 epiphany chips provide vastly more performance than anything else available to date with an architecture designed to scale and applicable to more than just embarrassingly parallel gpu tasks . citation needed e.g. it would be capable of running the actor model with many concurrent fully independent states . it is also suitable for dsp like tasks where data could be fed directly on chip from an fpga or other asic without having to create buffers in temporary memory as for a gpu making it ideal for robotics & other intelligent sensor applications . the architecture also allows parallella boards to be combined into a cluster with a fast inter chip emesh interconnect extending the logical grid of cores creating almost unlimited scaling potential . the 16 core parallella has roughly 5.0 gflops w and the 64 core epiphany iv made with 28 nm estimated as 50 gflops w single precision 24 and 32 board system based on them has 15 gflops w. 25 for comparison top gpus from amd and nvidia reached 10 gflops w for single precision in 2009 2011 timeframe . 26 see also edit sw26010 a chinese design featuring a similar architecture used in their sunway taihulight supercomputer partitioned global address space a similar memory model found in some hpc applications cell a multicore processor with scratchpad memory and inter core dma ibm truenorth a design by ibm with a radically different neuromorphic processor while having a similar network on chip extendable with a grid of chips kalray a company producing a similar network on chip risc processor aimed at workloads such as convolutional neural networks for vision again able to extend its grid between multiple chips vision processing unit a class of processor with significant overlapping features grvi phalanx an fpga risc v softcore with some similar features asynchronous array of simple processors numa references edit clark don may 3 2011 . startup has big plans for tiny chip technology . wall street journal . retrieved may 3 2011 . ibm says kilocore technology will outrun today s mobile processors . tom s hardware . 2006 . from rtl to gdsii in just six weeks . from rtl to gdsii in just six weeks . eetimes . 2010 . retrieved october 26 2010 . epiphany architecture reference manual . startup launches manycore floating point acceleration technology . startup launches manycore floating point acceleration technology . hpcwire . 2011 . retrieved may 3 2011 . epiphany multicore ip . example configurations . august 19 2012 . epiphany iii 16 core 65nm microprocessor e16g301 admin august 19 2012 epiphany iv 64 core 28nm microprocessor e64g401 admin august 19 2012 silicon devices adapteva linley gwennap adapteva more flops less watts . epiphany offers floating point accelerator for mobile processors . microprocessor report june 2011 michael feldman adapteva unveils 64 core chip hpcwire andreas olofsson epiphany documentation release update 46 first parallella user created video rick merritt adapteva kickstarts hundred dollar supercomputer eetimes september 27 2012 parallella supercomputing for everyone slidecast adapteva founder & ceo andreas olofsson september 28 2012 parallella a supercomputer for everyone by adapteva project page at kickstarter parallella a supercomputer for