improve it or discuss these issues on the talk page . learn how and when to remove these template messages a major contributor to this article appears to have a close connection with its subject . it may require cleanup to comply with wikipedia s content policies particularly neutral point of view . please discuss further on the talk page . april 2010 learn how and when to remove this template message this article needs additional citations for verification . please help improve this article by adding citations to reliable sources . unsourced material may be challenged and removed . april 2010 learn how and when to remove this template message learn how and when to remove this template message ensilica ltd. type private industry semiconductor industry founded 2001 headquarters wokingham berkshire uk products microprocessor cores website www.ensilica.com ensilica is a design services and ip core company based in wokingham uk . it is known for its esi risc configurable microprocessor cores for system on a chip designs . in addition it is a recognized supplier of communications ip under the esi comms family name . contents 1 history 2 esi risc 3 esi comms 4 external links history edit ensilica was formed in 2001 from a group of semiconductor professionals who had worked in engineering and management positions at a number of global telecommunications companies . their knowledge of communications asics established the company as a leading provider of design services to uk high technology industry . the company has grown at its wokingham site and now includes a regional expert design center in cambridge . the company regularly features in articles from electronics weekly cambridge wireless silicon south west and the national microelectronics institute . esi risc edit ensilica develops soft processor ip for use in synthesized chip designs specifically embedded systems under the family name esi risc . ensilica licenses its configurable processor core technology and provides three standard configurations esi 1600 esi 3200 and esi 3250 as well as custom architectures . esi 3250 soc architecture . the esi 1600 16 bit cpu core is a low cost low power processor ideal for integration into asic and or fpga designs . it offers similar performance to more expensive 32 bit cpus while having a system cost comparable to that of 8 bit cpus . significant power savings are possible compared to 8 bit cpus as applications require far fewer clock cycles to run . the esi 3200 32 bit cpu core is an extremely small low cost low power processor ideal for integration into asic and or fpga designs with on chip memories . the esi 3200 is particularly suited to embedded control applications . the esi 3250 32 bit cpu is the top of the range member in the esi risc family of processor cores . it is targeted specifically for applications with high performance and large memory requirements . for applications where high performance is required the five stage pipeline allows high clock frequencies to be achieved . while most instructions effectively execute in a single clock cycle the deep pipeline allows the c and c compiler to schedule independent instructions such that instructions that can take multiple cycles to execute appear to only take one clock cycle . static branch prediction is employed to minimize the cost of branch instructions . the esi risc instruction set includes arithmetic and logical instructions including barrel shift multiply and divide comparisons load and stores branches and calls as well as system level instructions to control interrupts and enter lower power states . there are also a number of optional instructions and addressing modes that can be selected should a specific application require them . a number of instructions are reserved to allow the user to utilize user defined logic via a simple interface . this allows for otherwise unobtainable performance to be reached for many software inner loops . instructions are encoded in either 16 or 32 bits depending upon the size of the operands and the type of instruction . all of the commonly used instructions can be encoded in 16 bits . this ensures that high code density is achieved while minimizing memory accesses to help conserve power . the toolchain for esi risc is based upon the industry standard gnu toolchain which includes an optimizing c and c compiler assembler linker debugger simulator and binary utilities . all these tools can be driven by the customizable eclipse ide . the debugger can connect to the target cpu either via jtag or a serial interface . complete c and c libraries are supplied . the toolchain is available for both windows and linux hosts . esi comms edit ensilica license a range of communications ip specifically for modern cofdm communication systems . these include critical demodulation and forward error correction modules such as fast fourier transform viterbi decoder and reed solomon decoder . these ip cores can be used standalone or integrated into a soc subsystem with the esi risc processor . external links edit official website a guide to cpu cores and processor ip . focusing on cpu dsp and gpu . third edition . kevin krewell and j. scott gardner april 2012 . section ensilica retrieved from https en.wikipedia.org w index.php title ensilica & oldid 722329083 categories companies established in 2001embedded microprocessorshidden categories wikipedia articles with possible conflicts of interest from april 2010articles needing additional references from april 2010all articles needing additional references navigation menu personal tools not logged intalkcontributionscreate accountlog in namespaces article talk variants views read edit view history more search navigation main pagecontentsfeatured contentcurrent eventsrandom articledonate to wikipediawikipedia store interaction helpabout wikipediacommunity portalrecent changescontact page tools what links hererelated changesupload filespecial pagespermanent linkpage informationwikidata itemcite this page print export create a bookdownload as pdfprintable version languages magyar edit links this page was last modified on 27 may 2016 at 11 32 . text is available under the creative commons attribution sharealike license ; additional terms may apply . by using this site you agree to the terms of use and privacy policy . wikipedia is a registered trademark of the wikimedia foundation inc. a non profit organization . privacy policy about wikipedia disclaimers contact wikipedia developers cookie statement mobile view