interconnect terminals
on chip interconnects
with the ability to integrate a large number of cores on a single chip research into on chip networks to facilitate communication becomes increasingly important . on chip networks seek to provide a scalable and high bandwidth communication substrate for multi core and many core architectures . high bandwidth and low latency within the on chip network must be achieved while fitting within tight area and power budgets . in this lecture we examine various fundamental aspects of on chip network design and provide the reader with an overview of the current state of the art research in this field . table of contents introduction interface with system architecture topology routing flow control router microarchitecture conclusions