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UNIVERSITY OF WISCONSIN-MADISON
Computer Sciences Department
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CS 537
Spring 2000
| | A. Arpaci-Dusseau
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| Quiz #7
March 28
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Probem 1: Segmentation
Consider a virtual memory architecture with the following parameters:
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Byte addresses
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30 bit virtual addresses
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Maximum segment size of 4 megabyte (MB)
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4 gigabytes of real memory
Show how a virtual address gets mapped into a real address.
Be sure to show
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how the various fields of each address are interpreted,
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the size of each field (in bits),
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the maximum number of entries the table could hold,
and
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where checks are made for invalid virtual addresses.
Draw and label a diagram to answer this question.
The Segment Table has 256 entries, with each entry being 54 bits.
Problem 2: Multi-Level Paging
Consider a virtual memory architecture with the following parameters:
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48 bit virtual addresses
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32K byte page size
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32 terabytes (TB) of real memory
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first and second level page tables are stored in real memory (RAM)
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all page tables can start only on a page boundary
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second level page tables should have a maximum size such that
they each can fit in a single page frame.
Show how a virtual address gets mapped into a real address.
Be sure to show
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how the various fields of each address are interpreted,
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the size of each field (in bits),
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the maximum number of entries each table could hold,
and
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the maximum size possible for each table (in bytes).
Draw and label a diagram to answer this question.
The first-level page table has 1M entries times 48 bits (6 bytes, 43 bits rounded up to
48, a multiple of 8 bits), so has a maximum size of 6 MB.
Each second-level page table has 8K entries (not 32K entries!).
The page size is 32KB and the second-level PTE has a PPN of 30 bits (rounded up
to 32 bits) or 4 bytes.
A 32KB page can hold 8K 4-byte entries.
4 bytes times 8K is 32KB.
The extra bits in any of these entries might be used for valid or read/write
bits.
Problem 3: Paging and TLB's
Consider a virtual memory architecture with the following parameters
(note that these are the same parameters from Quiz #8):
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48 bit virtual addresses
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32K byte page size
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32 terabytes (TB) of real memory
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page tables are stored in real memory
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page tables can start only on a page boundary
Add a TLB to the memory mapping architecture that is described above.
This cache should be
2-way set associative
and have
512 rows.
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On the next page draw a diagram of the TLB,
showing the size of each field in the TLB.
Indicate how bits of the VA are used for input to the TLB, and describe the
outputs from the TLB.
Include read/write protection bits for each page in your TLB.
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If your PTE's contain R/W protection bits, why do they also need to be included
in the TLB?
If an address hits in the TLB, it will bypass looking in the
page table.
If the R/W bits are only in the page table, we wouldn't be able to
check the permissions on pages whose addresses were in the TLB.
