Address

Computer Sciences Department
University of Wisconsin - Madison
1210 West Dayton Street
Madison, WI 53706

Department of Electrical and Computer Engineering
University of Wisconsin - Madison
1415 Engineering Drive
Madison, WI 53706

Office

3652 Engr. Hall

Phone

(608) 265-3826

E-mail

ericro@cs.wisc.edu

Research Area

Computer Architecture

Advisor

Professor J.E. Smith

Research Topics

• Kestrel Multiscalar Project
• Control Independence
• Trace Processors
• High Bandwidth Instruction Fetch Mechanisms
• Instruction-Level Parallelism (ILP)

"Control Independence in Trace Processors", Eric Rotenberg and James E. Smith, To appear in Proceedings of the 32nd Annual International Symposium on Microarchitecture, November 1999.
PDF version

"Trace Processors: Exploiting Hierarchy and Speculation", Eric Rotenberg, Ph.D. Thesis, University of Wisconsin - Madison, August 1999.

"AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors", Eric Rotenberg, Proceedings of the 29th Fault-Tolerant Computing Symposium, June 1999.

"A Trace Cache Microarchitecture and Evaluation", Eric Rotenberg, Steve Bennett, and James E. Smith, IEEE Transactions on Computers, Special Issue on Cache Memory, February 1999.

"A Study of Control Independence in Superscalar Processors", Eric Rotenberg, Quinn Jacobson, and James E. Smith

• HPCA-5 paper: Proceedings of the 5th Annual International Symposium on High Performance Computer Architecture, January 1999.
• Technical Report: University of Wisconsin - Madison Technical Report #1389, December 1998.
  

"Trace Processors", Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, and James E. Smith, Proceedings of the 30th Annual International Symposium on Microarchitecture, pp. 138-148, December 1997.

"Path-Based Next Trace Prediction", Quinn Jacobson, Eric Rotenberg, and James E. Smith, Proceedings of the 30th Annual International Symposium on Microarchitecture, pp. 14-23, December 1997.

"Assigning Confidence to Conditional Branch Predictions", Erik Jacobsen, Eric Rotenberg, and James E. Smith, Proceedings of the 29th Annual International Symposium on Microarchitecture, pp. 142-152, December 1996.

"Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching", Eric Rotenberg, Steve Bennett, and James E. Smith

• Micro-29 paper: Proceedings of the 29th Annual International Symposium on Microarchitecture, pp. 24-34, December 1996.
• Technical Report: University of Wisconsin - Madison Technical Report #1310, April 1996.
  

AR-SMT (FTCS-29)

Control Independence (HPCA-5)
(See slides 19 and 20 for new results: 3 factors that account for performance differences between ideal study and implementation study.)

Trace Processors (Micro-30)

Trace Cache (Micro-29)

Branch Prediction Confidence (Micro-29)