# Example Makefile for CS537-2, S2012

#-------------------------------------------------------------------------------
# specify the compiler to use
#-------------------------------------------------------------------------------
CC = gcc

#-------------------------------------------------------------------------------
# flags to be passed to the compiler
# -Wall: enable all warnings <-- in this course, you should ALWAYS use this flag
#
# for information about other possible options, read the man page for gcc
#
# in particular, you may find the -g flag useful; this flag produces debugging
# information which can be used by GDB 
#-------------------------------------------------------------------------------
CFLAGS = -Wall 

#-------------------------------------------------------------------------------
# flags to be passed to the linker
# for this assignment, you probably don't need any 
#-------------------------------------------------------------------------------
LFLAGS = 

#-------------------------------------------------------------------------------
# specify the executable file
#-------------------------------------------------------------------------------
TARGS = hello

#-------------------------------------------------------------------------------
# for convenience, we'll specify a make target 'all' that makes all targets
# 
# note that if you type 'make' it will build the target specified by the first
# rule in the file; in this case, that's 'all'
#-------------------------------------------------------------------------------
all: $(TARGS)

#-------------------------------------------------------------------------------
# general layout of Makefile rules
# target: dependencies
# 	command
#-------------------------------------------------------------------------------

#-------------------------------------------------------------------------------
# a rule to build our executable, hello
# this rule links together a set of object files (the dependencies) into a 
# single executable (the target)
#
# target: hello
# dependencies: hello.o
#-------------------------------------------------------------------------------
hello: hello.o
	$(CC) $(LFLAGS) -o hello hello.o

#-------------------------------------------------------------------------------
# Note: this could have been written more generally as:
# hello: hello.o
# 	$(CC) $(LFAGS) -o $@ hello.o
#
# or even more simply as:
# hello: %.o
# 	$(CC) $(LFAGS) -o $@ $^
#-------------------------------------------------------------------------------

#-------------------------------------------------------------------------------
# a rule to compile a .c file into an object file (.o)
#
# we'll use wildcards and patterns to write a general rule
# %.o: matches any string with a .o extension
# %.c: a .c file with the same basename as the .o file provided as the target
# $^: gets replaced with all dependencies
#
# target: a .o file
# dependencies: the corresponding .c file
#
# for instance, if we type "make hello.o," the Makefile will check one 
# dependency, hello.c, and run the command
# 	gcc -Wall -c hello.c
# and produce the file hello.o
#-------------------------------------------------------------------------------
%.o: %.c
	$(CC) $(CFLAGS) -c $^

#-------------------------------------------------------------------------------
# for future reference, here are some other patterns you can use:
# $@: replaced with the name of the target
# $<: replaced with the first dependency
# $^: replaced with all dependencies (skips duplicates)
# $+: replaced with all dependencies (includes duplicates)
# $?: replaced with dependencies newer than target
#-------------------------------------------------------------------------------

#-------------------------------------------------------------------------------
# we'll also build a target that "cleans" out the directory, removing targets
# and other intermediate files 
#-------------------------------------------------------------------------------
.PHONY: clean

clean:
	rm -f *~ *.o $(TARGS)