@COMMENT This file was generated by bib2html.pl <https://sourceforge.net/projects/bib2html/> version 0.94
@COMMENT written by Patrick Riley <http://sourceforge.net/users/patstg/>
@COMMENT None
@InProceedings{isca03,
  author =       "Karthikeyan Sankaralingam and Ramadass Nagarajan and Haiming Liu and Changkyu Kim and Jaehyuk Huh and Stephen W. Keckler and Doug Burger and Charles R. Moore",
  title =        "{Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture}",
  booktitle =    "Proceedings of the 30th Annual International Symposium on Computer Architecture",
  pages =        {422--433},
  year =         2003,
  month =        {June},
  abstract={This paper describes the polymorphous TRIPS architecture which
can be configured for different granularities and types of
parallelism.  TRIPS contains mechanisms that enable the processing
cores and the on-chip memory system to be configured and combined in
different modes for instruction, data, or thread-level parallelism.
To adapt to small and large-grain concurrency, the TRIPS architecture
contains four out-of-order, 16-wide-issue Grid Processor cores, which
can be partitioned when easily extractable fine-grained parallelism
exists.  This approach to polymorphism provides better performance
across a wide range of application types than an approach in which
many small processors are aggregated to run workloads with irregular
parallelism. Our results show that high performance can be obtained in
each of the three modes--ILP, TLP, and DLP--demonstrating the
viability of the polymmorphous coarse-grained approach for future
microprocessors.},
  bib2html_dl_pdf = "http://www.cs.wisc.edu/~karu/docs/papers/utexas/isca03-trips.pdf",
  bib2html_pubtype = {Refereed Conference},
  bib2html_rescat = {Architecture},
  bib2html_extra_info = {This is a test of the extra info broadcasting system.}
}