@COMMENT This file was generated by bib2html.pl <https://sourceforge.net/projects/bib2html/> version 0.94
@COMMENT written by Patrick Riley <http://sourceforge.net/users/patstg/>
@COMMENT None
@InProceedings{isscc03,
  author =       "Stephen W. Keckler and Doug Burger and Charles R. Moore and Ramadass Nagarajan and Karthikeyan Sankaralingam and Vikas Agarwal and M.S. Hrishikesh and Nitya Ranganathan and Premkishore Shivakumar",
  title =        "{A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems}",
  pages =        {},
  booktitle =    "Proceedings of the 2003 International Solid-State Circuits Conference",
  year =         2003,
  month =        {February},
  abstract={
This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15 times/ more instructions per clock than conventional superscalar architectures.},
  bib2html_dl_html = "http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=27661&arnumber=1234252&count=236&index=56",
  bib2html_pubtype = {Refereed Conference},
  bib2html_rescat = {Architecture,Hardware},
  bib2html_extra_info = {This is a test of the extra info broadcasting system.}
}