Primary contact for this homework: Pradip Vallathol [pradip16 at cs dot wisc dot edu]
You must do this homework in groups of two. Please write the full name and the student id of each member on every page and staple multiple pages together.
Problem 1 (4 points)
Implement a full adder with a 3-to-8 decoder and two 4-input OR gates. Use Figure 1 to represent a 3:8 decoder.
Hint: Use the table in Fig 3.14 on page 62 of the textbook.
Problem 2 (6 points)
Consider the State Diagram shown below. Each state is denoted as a 2-bit value, the values on the arrows represent the input, and X in each state represents the output.
- Fill out the Output truth table for the above state diagram.
| State | Output |
| 00 | 1 |
| 01 | 0 |
| 10 | 0 |
| 11 | 1 |
- Fill out the next state logic in a State table for the above state diagram.
Current
State | Input | Next
State |
| 00 | 0 | 01 |
| 00 | 1 | 10 |
| 01 | 0 | 10 |
| 01 | 1 | 11 |
| 10 | 0 | 11 |
| 10 | 1 | 01 |
| 11 | 0 | 00 |
| 11 | 1 | 00 |
Problem 3 (6 points)
Design a finite state machine (FSM) that recognizes the pattern "1101". The input to the FSM is a sequence of binary bits in series. When the FSM has 1101 as inputs in successive bits, it should output 1. Otherwise, the output should be 0. The bits are read from left to right.
For example:
Input sequence: 1 1 0 1 1 0 1 0 1 1 0 1
FSM output : 0 0 0 1 0 0 1 0 0 0 0 1
where S0 is the initial state and Z is the output.
Problem 4 (6 points)
Consider a machine which implements an instruction set architecture (ISA) in which every instruction is 16 bits long and has the following format:
Where DR = Destination register, SR = Source Register, and IMMVAL = Immediate Value. The fields DR, SR are represented using the same number of bits.
-
If the maximum number of instructions supported by the ISA is 25, how many bits are used to represent the OPCODE field?
24 < 25 < 25. So, 5 bits are required.
-
If 3 bits are used to represent both DR and SR, how many registers are supported by the ISA?
23 = 8 registers
-
If IMMVAL is always a 2's complement value, what is the range of of values that can be represented in the IMMVAL field?
Number of bits for IMMVAL = 16 - 5 - (2*3) = 5 bits. So range is -16 to 15.
Problem 5 (2 points)
Suppose the number of address bits in memory is increased by 4 bits. By what factor should the addressability change relative to the original one so that the memory size remains the same?
Address bits increased by 4 bits = number of memory locations increased by 24 = 16.
Memory size = (addressability) * (number of memory locations)
So for memory size to remain the same, addressability has to be made 1/16th (or reduced by a factor of 16).
Problem 6 (3 points)
Given than an instruction takes 4 cycles to complete execution in a machine which has a clock period of 5 ns, find the following:
- Clock frequency of the machine
1/(5 * 10-9) = 109/5 = 200 MHz
- Number of instructions that can be executed in one second
200M cycles per second, 4 cyles per instruction
So number of instructions per second = 200M/4 = 50M instructions in one second.
Problem 7 (3 points)
Consider the 6 stage Instruction Cycle as discussed in the lecture (or Section 4.3.2 or your textbook). State briefly what happens in each stage of the instruction cycle (one sentence per stage) during the execution of the following instruction. Explicitly state if a stage is not required during the execution.
ADD the values of two registers R1 and R2 and write the result to a register R3.
Fetch: Fetch the instruction into IR and increment PC.
Decode: Understand that the instruction is supposed to do addition, what registers are to be added and where to store the sum.
Evaluate Address: Nothing (no memory access).
Fetch Operands: Fetch the values of registers R1 and R2.
Execute: compute the sum of the values fetched from the registers.
Store Result: Store the sum into register R3.
