Homework 4 // Due at Lecture Wed Mar 07
You may do this homework in a group of two students from the same 252 section and
turn in one solution at lecture with BOTH students names at the top.
First contact for questions is TA Marc de Kruijf at: dekruijf@cs.wisc.edu
Problem 1
Problem 3.30 on page 92 of ItCS.
Problem 2
On a highway, there is a toll booth. A camera mounted on the toll booth takes
license plate pictures of every second car that does not pay the toll. This
scenario can be modeled using a finite state machine.
- Draw the finite state machine diagram for this problem as in Figure
3.31 of ItCS. The input to your finite state machine is whether or not (1
or 0) the car payed the toll, and the output is whether or not (1 or 0) the
camera takes a picture. The clock cycles once per car.
- Draw a block diagram of the sequential circuit implementation as
in Figure 3.32 (a) in ItCS.
- Draw the combinational logic circuit of your block diagram as in Figure 3.32 (b)
in ItCS.
Problem 3
Problem 4.3 on page 111 of ItCS.
Problem 4
Problem 4.5 on page 111 of ItCS, omitting part b (3), and using the following memory table instead of the one provided:
Address |
Data |
0000 |
0110 0110 0100 0101 |
0001 |
1111 1111 1101 0111 |
0010 |
0010 1001 0000 0000 |
0011 |
0000 0000 0001 0010 |
0100 |
0011 0010 0010 0001 |
0101 |
0000 0000 0000 0010 |
0110 |
1001 0100 1110 0010 |
0111 |
0011 1110 1011 0111 |
Problem 5
Problem 4.8 on page 112 of ItCS, assuming 120 opcodes and 225 registers (the numbers are swapped).
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