CS/ECE 552: Introduction to Computer Architecture
Section 2 for Fall 2000-2001
URL: http://www.cs.wisc.edu/~markhill/cs552/Fall2000/
Last updated by
Brandon Schwartz
on
Mon Dec 4 11:32:53 CST 2000
Computer
architecture is the science and art of selecting and interconnecting
hardware components to create a computer that meets functional,
performance and cost goals. In this course, students will learn how
to completely design a correct single processor computer, including
processor datapath, processor control, memory systems, and I/O. We
will learn that no magic is required to make a computer work.
CS/ECE 552 serves students two ways. First, for those who will
continue in computer architecture, it lays foundation of detailed
implementation experience necessary to make meaningful the
quantitative tradeoffs found in CS/ECE 752 and 757. Second, for those
students not continuing in computer architecture, it unifies concepts
introduced in CS/ECE 352 and 354 and solidifies an intuition about why
hardware is as it is.
CS/ECE assumes that you are familiar with the material in the prerequites
CS/ECE 352 and 354, especially:
- Knowledge of a high-level language
- Understanding of computer data structures
- Knowledge of stack mechanisms and procedure calls
- Understanding of assembly language programming: opcodes, operands, etc.
- Boolean logic design techniques
- Realization of boolean functions using AND, OR, NOT, XOR, NAND,
NOR gates and appropriate minimization techniques
- Logic building blocks: flip-flops, multiplexors, decoders,
shift registers
Office: 6373 Comp Sci and Stat
Email: 
Office hours: Monday 2:30-3:30 PM, Wednesday 1:30-2:30 PM,
or by appointment
Office: 3360 Comp Sci and Stat
Email: baschwar@cs.wisc.edu
Phone: Please use email!
Office hours: Tuesday 2:30-3:30 PM, Thursday 1:20-2:20 PM,
or by appointment
John L. Hennessy and David A. Patterson,
Computer Organization and Design: The Hardware and Software Interface
Morgan Kaufmann Publishers, Second Edition, 1996.
- Web Materials for Text
- Peter J. Ashenden, The Student's Guide to VHDL
- Peter J. Ashenden, The Designer's Guide to VHDL
Time: 11:00 - 12:15 Monday, Wednesday, and Friday
Place: 103 Psychology
This class is over-scheduled. A three credit course needs
only two lectures per week. I will use the extra scheduling to
"front load" the course and to allow more time for the project.
For this reason, we can cancel approximately 15 lectures.
Lectures canceled are:
- Fri, Oct 13
- Fri, Oct 27
- Mon & Wed, Nov 13 & 15
- Fri Nov 24 (for Thanksgiving)
- Last Two Weeks, Dec 3-15 (six lectures)
- Fri Nov 17, Wed Nov 22 (day before Thanksgiving), and Fri Dec 1.
Approximate Lecture Notes: (Univ. of Wisconsin-Madison only)
There will be about six homework assignments, approximately one
assignment every two weeks. Assignments will not be weighted equally.
The approximate weights of each assignment will be specified when the
assignment is handed out. Assignments will be due in class on the
due date. NO LATE ASSIGNMENTS WILL BE ACCEPTED, except under extreme
non-academic circumstances discussed with the instructor at least one
week before the assignment is due.
The first three assignments (and the project)
will require the use of the Mentor Graphics design automation tools.
Students will have accounts to run the Mentor tools in CS on nova
workstations in rooms 1358, 1368, and 1347/1349. The novas are Sun
Ultra 10 (SPARC v9) workstations running Solaris 7. We do not support
the running of Mentor on any other machines.
Students new to Unix should attend to CSL orientation session
during the first two weeks of class (see posters in CS building)
and but the CS 1000 handout at the DoIT tech store.
Homeworks Assignments and Selected Solutions: (Univ. of Wisconsin-Madison only)
- Online list of demo times.
- FAQ file.
-
The project memory file is available at
/p/course/cs552-markhill/public/html/Project/mem.vhdl. Edit the
file (after you copy it to your mentor/vhdlcode directory) to point
to your own memory files. The assember for creating memory files
and instructions for its use are available at
/p/course/cs552-markhill/public/html/Project/Asm
- Progress Report
- Due 11:00 AM Monday, 11/13/2000
- Each group needs to turn in a typed report (1 page
single-spaced max) discussing how things are going. In addition,
you need to turn in the state diagrams of your CPU controller along
with a printout of the top level datapath for the entire design. This
is worth 5% of your grade. If your hardware design is not complete,
create empty symbols to incorporate into your top level datapath. The
datapath should approximately resemble the figure 5.33 on page 383 of
Hennessy and Patterson.
- Instruction Set Specification.
- Grading
Guidelines and Deadlines.
There will be two in-class exams at the 40% and 80% point of the
semester. They are tentatively scheduled for:
- Mon, Oct 11th
- Wed, Nov 29th
There will be no final exam, so you can concentrate on your project.
University policy on incompletes and academic misconduct (inappropriate
activity, whole handbook)
will be followed strictly. Besides, the only person you would be
cheating is yourself.
Some guidelines regarding misconduct: If you have a question about the
phrasing of a problem, assignment, or specification, please email the
TA. Often, the first question will prompt a reply to the class list,
so you will be doing your peers a favor. If you have a question about
a tool, (Mentor, VHDL, etc.,) feel free to ask your peers how the tool
works BUT DO NOT USE THIS OPPORTUNITY TO OBSERVE THEIR WORK! THIS IS
MISCONDUCT. Contrawise, if you are asked a question regarding a tool,
please help the questioner. If your peers are not available or not
able to help, then you can see the TA. If you have a question about
how to do a problem, assignment, project, etc. PLEASE SEE THE TA. For
all other academic help or questions, SEE THE TA. If you are not sure
whether assistance would count as academic misconduct, SEE THE TA.
Remember, BOTH the seeking AND the responding parties are responsible for
academic misconduct.
- 20% Homework
- 25% Project
- 25% Midterm I
- 30% Midterm II
| Week of |
Monday |
Wednesday |
Friday |
| Sep 4 |
-- |
Introduction (1) |
Performance (2) |
| Sep 11 |
Instructions (3) |
Instructions |
Arithmetic (4.1-4.5) |
| Sep 18 |
Arithmetic |
Datapath (5) |
Control (5) |
| Sep 25 |
Control |
Control |
Control |
| Oct 2 |
VHDL |
Slop |
Review |
| Oct 9 |
Slop |
Midterm I |
Pipelining (6) |
| Oct 16 |
Pipelining |
Pipelining |
-- |
| Oct 23 |
Pipelining |
Memory (7) |
-- |
| Oct 30 |
Memory |
Memory |
Memory |
| Nov 6 |
Memory |
Arithmetic (4.6+) |
Arithmetic |
| Nov 13 |
-- |
-- |
I/O (8) |
| Nov 20 |
I/O |
Slop |
-- |
| Nov 27 |
Review |
Midterm II? |
Blue Sky |
| Dec 4 |
-- |
-- |
-- |
| Dec 11 |
-- |
-- |
-- |
Computer Sciences Department
College of Letters and Science
University of Wisconsin - Madison
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