CS/ECE 552 Introduction to Computer Architecture Fall 2006 Section 2 Instructor Mark D. Hill and T. A. Derek Hower URL: http://www.cs.wisc.edu/~markhill/cs552/Fall2006/

Homework 2 // Due at Lecture Tue Oct 3

Problem 1

Design a 16-bit barrel shifter using Mentor's design architect. The barrel shifter will perform four types of shifts: rotate left, rotate right, shift left logical, and shift right logical. Additionally, the shifter should be able to shift the operand any arbitrary number of bits in one pass.

The design of the barrel shifter should be heirarchal in nature and be constructed almost exclusively from 2-1 and 4-1 multiplexers.

The external interface to the barrel shifter should be exactly as follows:

• Inputs:
• In[15:0] - input operand
• Shamt[3:0] - the number of bit positions to shift
• Op[1:0] - opcode (see Table 1)
• Outputs:
• Out[15:0] - shift result

You should hand in:

1. Schematic sheets and symbol sheets of all the blocks that you designed.
2. Annotated simulation trace output of the complete design. Pick representative cases for your simulation input.
3. A short justification of your testing methodology.

Problem 2

Design a 16-bit Arithmetic Logic Unit using Mentor. Operations to be performed are 2's Complement ADD, bitwise-OR, bitwise-XOR, bitwise-AND, and all shifting operations described in Problem 1. In addition, it must have the ability to invert either of its data inputs before performing the operation and have a carry-in input. Another input line determines whether the arithmetic to be performed is signed or unsigned . For the addition operation, design a carry look-ahead (CLA) adder.

The external interface of the ALU should be exactly as follows:

• Inputs:
• InA[15:0] - first operand
• InB[15:0] - second operand
• cin - carry-in bit
• Op[2:0] - opcode (see Table 2)
• invA - when set, invert operand A
• invB - when set, invert operand B
• sign - when set, perform signed addition. Otherwise perform unsigned.
• Outputs:
• Out[15:0] - ALU result
• ofl - when set, indicates an overflow occurred
• zero - when set, the result is exaclty zero

Assume the addition operands are in two's complement form.

Use a hierarchical design and simulate each block by itself before you try the complete design.

You should hand in:

1. Schematic sheets and symbol sheets of all the blocks that you designed. You may exclude any blocks that remain unmodified from Problem 1.
2. Annotated simulation trace output of the complete design. Pick representative cases for your simulation input.
3. A short justification of your testing methodology.
4. In a few words, describe why each signal in the list of inputs/outputs is useful in the context of a microprocessor ALU. You may exclude the very obvious signals InA, InB, and Out.

Problem 3

Problem 2.52 on CD of COD3e: In More Depth Use this instruction sequence instead of the one given:

Problem 4

Problem 2.57 on CD of COD3e: In More Depth Use the following loop instead of the one given:

Problem 5

See page B-43 on CD of COD3e: Chapter/Appendix Answer the problem using these operands instead of the ones given:

Problem 6

Problem 4.10 on Page 273 of COD3e

Problem 7

Problem 4.11 on Page 274 of COD3e. Please show all work.