CS/ECE 552 Introduction to Computer Architecture Fall 2006 Section 2 Instructor Mark D. Hill and T. A. Derek Hower URL: http://www.cs.wisc.edu/~markhill/cs552/Fall2006/

Homework 3 // Due at Lecture Thurs Oct 12

Problem 1

Redo the ALU from Homework #2 in Verilog using the same specifications. Use the following module template for your top level design:

The Verilog you write for this assignment should mimic the schematic design created earlier, i.e. each symbol created in Design Architect should have a corresponding module in Verilog.

You should thoroughly test your design. This does not mean you should exhaustively test your design; doing so would result in over 2^57 input combinations--hardly practical in anyone's lifetime. Rather, you should develop a sound testing strategy that uses "representative" forces for larger classes of input combinations. Your approach should include both common and boundary test cases.

Automate your simulations using either DO batch files or Tcl scripts (or a combination of both) as described in the ModelSim tutorial.

You should hand in:

1. Electronic copies of all Verilog, DO, and/or Tcl files used in your design. Submit the files by copying them to ~cs552-2/public/dropbox/HW3/P1/<your login id>.
2. A brief description of your testing strategy and annotated hard copies of representative test cases (may be either simulation wave traces or scripted text output). Be sure to explain why the test cases you chose are good representations. Turn in only the minimal set of simulation results needed to reasonably prove the correctness of your design.

Problem 2

Using Verilog, write, compile and simulate a six state saturating counter. The counter should take as input a clock and a reset line, and output a 3-bit wide bus. Reset is synchronous and sets the output to 0 at the rising edge of the clock. The output should increment every clock cycle until it reaches its saturation value (5, i.e. 101 in binary) and then continue to output the maximum value until reset. Use the following module template for your top level design:

The reset line is active high, i.e. a logical value of 1 will reset the counter, while a logical value of 0 will let the counter increment. If reset is high while the counter is still counting, the output should reset to 0. If reset is held high, the counter should hold at 0. All state changes should occur on the clock's rising edge.

Generate the clock using a single force statement. Consult the ModelSim help documentation to see how this is done.

You should use the D-flipflop found here in your design.

You should hand in:

1. Electronic copies of all Verilog, DO, and/or Tcl files used in your design. Submit the files by copying them to ~cs552-2/public/dropbox/HW3/P2/<your login id>.
2. Results of an exhaustive simulation, in the form of either an annotated simulation waveform or script output.

Problem 3

Implement a sequence detector similar to the one in Homework 1 using this pattern: 11011001. Use a minimal number of D-flipflops. Use Verilog to specify the circuit. You design will have three inputs (in, clk, rst) and two outputs (match and err). (The "err" output is a standard way of indicating hardware errors or illegal states; we'll get in the habit of using it, though in this case it will only be driven if there are states which are supposed to be impossible to get into.) Use the following Verilog template for your top-level design:

Produce the clock signal with a single force statement.

You should hand in:

1. Electronic copies of all Verilog, DO, and/or Tcl files used in your design. Submit the files by copying them to ~cs552-2/public/dropbox/HW3/P3/<your login id>.
2. Annotated simulation results, in the form of a simulation wave trace or script output, that shows the design working. Your results should also show that sequences which closely resemble the target input do not trigger a false match.

Problem 4

Consider a single-cycle computer design such as the one in Figure 5.17 of the text (page 307). Assume a MIPS-like instruction set. Suppose you had just completed such a design, and now the compiler group has come to you with a small list of additional instructions they would like you to add. How would you respond? Order the list from easiest to most difficult to add, based on the number of things that would have to change in the datapath; briefly indicate for each one what those changes would be.

1. "Split Register": This instruction would read an operand from $rs and move its lower half to $rd with the upper half set to zero. It would also take the upper half of $rs, shift it right 16 bits (with zero fill), and write it to $rt.
2. "Bit Equal": This instruction does a bit-for-bit compare between two registers. For each bit i, if bit i of $rs is equal to bit i of $rt, set bit i of $rd; otherwise set bit i of $rd to zero.
3. "Replace Under Mask": This instruction uses $rt to select which bits of $rs to replace with bits from the literal field. For each bit of $rt that is a zero, the result comes from the corresponding bit of $rs; for each bit that is a one, the result comes from the sign-extended 16-bit literal. The result is written to $rd.

Problem 5

For this problem, you do not need to use mentor or Verilog; just draw the designs (neatly!) on paper. First, design a 4-bit ripple-carry adder; as a building block use squares representing full adders. (You may use a printout from Homework 1.) Next, draw an 8-bit carry-select adder, using as building blocks 4-bit ripple-carry adders and 2:1 muxes.

Now, calculate the delay at output S5 of the carry-select adder. To do this, you will need to know the gate design of the full adder and the 2:1 mux; see the homework 1 solution. You will also need to know the delay function:

where n is the number of inputs to the gate.

Assume that all inputs to your design are available at time zero. Calculate (and mark on your paper) the pertinent critical-path delays through the basic building blocks, through your ripple adder, and finally to S5 of the entire design.