CS/ECE 552 Introduction to Computer Architecture Fall 2006 Section 2 Instructor Mark D. Hill and T. A. Derek Hower URL: http://www.cs.wisc.edu/~markhill/cs552/Fall2006/

CS/ECE 552 Final Project Description

WISC-FL06 Instruction Set Architecture

1. Instruction Summary

Formats

WISC-SP06 supports instructions in four different formats: J-format, 2 I-formats, and the R-format. These are described below.

1. J-format

The J-format is used for jump instructions that need a large displacement.

Jump Instructions

The Jump instruction loads the PC with the value found by adding the PC of the next instruction (PC+2, not PC+4 as in MIPS) to the sign-extended displacement.

The Jump-And-Link instruction loads the PC with the same value and also saves the address of the next sequential instruction (i.e., PC+2) in the link register R₇.

The syntax of the jump instructions is:

• J    displacement
• JAL  displacement

2. I-format

I-format instructions use either a destination register, a source register, and a 5-bit immediate value; or a destination register and an 8-bit immediate value.  The two types of I-format instructions are described below.

I-format 1 Instructions

The I-format 1 instructions include XOR-Immediate, ANDN-Immediate, Add-Immediate, Subtract-Immediate, Rotate-Left-Immediate, Shift-Left-Logical-Immediate, Shift-Right-Arithmetic-Immediate, Shift-Right-Logical-Immediate, Load, Store, and Store with Update.

The ANDNI instruction loads register R_d with the value of the register R_s AND-ed with the one's complement of the zero-extended immediate value. (It may be thought of as a bit-clear instruction.)  ADDI loads register R_d with the sum of the value of the register R_s plus the sign-extended immediate value.  SUBI loads register R_d with the result of subtracting register R_s from the sign-extended immediate value.  (That is, immed - R_s, not R_s - immed.)  Similar instructions have similar semantics, i.e. the logical instructions have zero-extended values and the arithmetic instructions have sign-extended values.

For Load and Store instructions, the effective address of the operand to be read or written is calculated by adding the value in register R_s with the sign-extended immediate value.  The value is loaded to or stored from register R_d. The STU instruction, Store with Update, acts like Store but also writes R_s with the effective address.

The syntax of the I-format 1 instructions is:

• ADDI  R_d, R_s, immediate
• SUBI  R_d, R_s, immediate
• XORI  R_d, R_s, immediate
• ANDNI R_d, R_s, immediate
• ROLI  R_d, R_s, immediate
• SLLI  R_d, R_s, immediate
• RORI  R_d, R_s, immediate
• SRLI  R_d, R_s, immediate
• ST    R_d, R_s, immediate
• LD    R_d, R_s, immediate
• STU   R_d, R_s, immediate

I-format 2 Instructions

The Load Byte Immediate instruction loads R_s with a sign-extended 8 bit immediate value.

The Shift-and-Load-Byte-Immediate instruction shifts R_s 8 bits to the left, and replaces the lower 8 bits with the immediate value.

The format of these instructions is:

• LBI  R_s, signed immediate
• SLBI R_s, unsigned immediate

The Jump-Register instruction loads the PC with the value of register R_s + signed immediate.  The Jump-And-Link-Register instruction does the same and also saves the return address (i.e., the address of the JALR  instruction plus one) in the link register R₇. The format of these instructions is

• JR    Rs, immediate
• JALR  Rs, immediate

The branch instructions test a general purpose register for some condition. The available conditions are: equal to zero, not equal to zero, less than zero, and greater than or equal to zero. If the condition holds, the signed immediate is added to the address of the next sequential instruction and loaded into the PC. The format of the branch instructions is

• BEQZ Rs, signed immediate
• BNEZ Rs, signed immediate
• BLTZ Rs, signed immediate
• BGEZ Rs, signed immediate

3. R-format

R-format instructions use only registers for operands.
 

ALU and Shift Instructions

The ALU and shift R-format instrucions are similiar to I-format 1 instructions, but do not require an immediate value.  In each case, the value of R_t is used in place of the immediate.  No extension of its value is required.  In the case of shift instructions, all but the 4 least-significant bits of R_t are ignored.

The ADD instruction performs signed addition. The SUB instruction subtracts R_s from R_t. (Not R_s - R_t.) The set instructions SEQ, SLT, SLE instructions compare the values in R_s and R_t and set the destination register R_d to 0x1 if the comparison is true, and 0x0 if the comparison is false. SLT checks for R_s less than R_t, and SLE checks for R_s less than or equal to R_t.   (R_s and R_t are two's complement numbers.) The set instruction SCO will set R_d to 0x1 if R_s plus R_t would generate a carry-out from the most significant bit; otherwise it sets R_d to 0x0. The Bit-Reverse instruction, BTR, takes a single operand R_s and copies it to R_d, but with a left-right reversal of each bit; i.e. bit 0 goes to bit 15, bit 1 goes to bit 14, etc.

The syntax of the R-format ALU and shift instructions is:

• ADD  R_d, R_s, R_t
• SUB  R_d, R_s, R_t
• ANDN R_d, R_s, R_t
• ROL  R_d, R_s, R_t
• SLL  R_d, R_s, R_t
• ROR  R_d, R_s, R_t
• SRL  R_d, R_s, R_t
• SEQ  R_d, R_s, R_t
• SLT  R_d, R_s, R_t
• SLE  R_d, R_s, R_t
• SCO  R_d, R_s, R_t
• BTR  R_d, R_s

4. Special Instructions

Special instructions use the R-format. The HALT instruction halts the processor.  The HALT instruction and all older instructions execute normally, but the instruction after the halt will never execute. The PC is left pointing to the instruction directly after the halt.

The No-operation instruction occupies a position in the pipeline, but does nothing.

The syntax of these instructions is:

• HALT
• NOP

The RTI instruction should remain equivalent to NOP until the rest of the design has been completed and thoroughly tested.

RTI returns from an exception by loading the PC from the value in the EPC register.

The syntax of this instruction is:

• RTI