CS/ECE 552: Introduction to Computer Architecture
Section 2 for Fall 1997-1998
URL: http://www.cs.wisc.edu/~markhill/cs552/
Computer architecture is the science and art of selecting and
interconnecting hardware components to create a computer that meets
functional, performance and cost goals. In this course, students will
learn how to completely design a correct single processor computer,
including processor datapath, processor control, memory systems, and
I/O. We will learn that no magic is required to make a computer work.
CS/ECE 552 serves students two ways. First, for those who will
continue in computer architecture, it lays foundation of detailed implementation
experience necessary to make meaningful the quantitative tradeoffs found in
CS/ECE 752 and 757. Second, for those students not continuing in computer
architecture, it unifies concepts introduced in CS/ECE 352 and 354 and
solidifies an intuition about why hardware is as it is.
CS/ECE assumes that you are familiar with the material in the prerequites
CS/ECE 352 and 354, especially:
- Knowledge of a high-level language
- Understanding of computer data structures
- Knowledge of stack mechanisms and procedure calls
- Understanding of assembly language programming: opcodes, operands, etc.
- Boolean logic design techniques
- Realization of boolean functions using AND, OR, NOT, XOR, NAND,
NOR gates and appropriate minimization techniques
- Logic building blocks: flip-flops, multiplexors, decoders,
shift registers
Office: 6373 Comp Sci and Stat
Email: 
Office hours: 1:30-2:30 PM Monday and Thursday
or by appointment
Office: 1346 Comp Sci and Stat
Phone: 262-9822
Email: ashisht@cs.wisc.edu
Office hours: 4:00-5:00 PM Wednesday and Friday
or by appointment
John L. Hennessy and David A. Patterson,
Computer Organization and Design: The Hardware and Software Interface
Morgan Kaufmann Publishers, First Edition, 1993.
- Peter J. Ashenden, The Designer's Guide to VHDL - On reserve at Wendt library
- J. P. Hayes, Computer Architecture and Organization
- Rafiquzzaman and Chandra, Modern Computer Architecture
- J. Wakerly, Digital Design Principles and Practices
- V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization
Time: 11:00 - 12:15 Tuesdays and Thursdays
Place: 1325 Comp Sci and Stat
There will be about six homework assignments, approximately one
assignment every two weeks. Assignments will not be weighted equally.
The approximate weights of each assignment will be specified when the
assignment is handed out. Assignments will be due in class on the
due date. NO LATE ASSIGNMENTS WILL BE ACCEPTED, except under extreme
non-academic circumstances discussed with the instructor at least one
week before the assignment is due.
The first three assignments (and the project)
will require the use of the Mentor Graphics design automation tools.
Students will have accounts to run the Mentor tools in CS, on Sun
workstations. These workstations are in rooms 1358, 1363, and 1368 in
CS. The "sol" machines have faster processors than the "vegas" machines.
Both sol and vegas machines have 64MB of memory; all other machines have 32MB.
For Mentor, the extra memory may improve performance more than the
faster processor.
The project is not yet ready. To get an idea of what it might be like, check
out last semester's project and deadlines.
There are two documents describing the project:
-
Instruction Set Specification
-
Grading Guidelines and Deadlines
There will be one midterm and one final exam.
The midterm exam will (tentatively) be in class on
October 21, 1997.
The final exam will be during the slot given in the timetable:
Monday, December 15, 1997 from 5:05 PM to 7:05 PM in a room to
be announced late in the semester.
Please advise me by Sep 21 if you have a conflict with either of
these times.
University policy on incompletes and academic misconduct (inappropriate
activity, whole
handbook) will be followed strictly.
- 20% Homework
- 25% Project
- 20% Midterm
- 35% Final
| Date(s) |
Chapter |
Topic |
| --, -- | A, B, D | Assumed background |
| 9/2, 9/4 | 1, 2 | Introduction, Performance |
| 9/9, 9/11 | 3 | Instructions |
| 9/16, 9/18 | 4.1-4.5 | Arithmetic |
| 9/23, 9/25 | 5 | cont., Datapath |
| 9/30, 10/1 | 5, C | Control |
| 10/7, 10/9 | -- | cont. |
| 10/14, 10/16 | -- | VHDL, Review 1-5 |
| 10/21, 10/23 | 1-5, 6 | MIDTERM, Pipelining |
| 10/28, 10/30 | 6 | Pipelining |
| 11/4, 11/6 | 7 | Memory Hierarchies |
| 11/11, 11/13 | -- | cont. |
| 11/18, 11/20 | 4.6-4.11 | More Arithmetic |
| 11/25, -- | -- | cont. |
| 12/2, 12/4 | 8 | I/O |
| 12/9, 12/11 | -- | Slop, Blue Sky |
Last updated by
Mark Hill
at
Tue Sep 2 08:12:33 CDT 1997