


DINEROIII()         UNIX Programmer's Manual          DINEROIII()



NNNNAAAAMMMMEEEE
     dineroIII - uniprocessor cache simulator, version III

SSSSYYYYNNNNOOOOPPPPSSSSIIIISSSS
     ddddiiiinnnneeeerrrrooooIIIIIIIIIIII -b block_size -u unified_cache_size -i
     instruction_cache_size -d data_cache_size [ other_options ]

DDDDEEEESSSSCCCCRRRRIIIIPPPPTTTTIIIIOOOONNNN
     _d_i_n_e_r_o_I_I_I is a trace-driven cache simulator that supports
     sub-block placement.  Simulation results are determined by
     the input trace and the cache parameters.  A trace is a fin-
     ite sequence of memory references usually obtained by the
     interpretive execution of a program or set of programs.
     Trace input is read by the simulator in _d_i_n format
     (described later).  Cache parameters, e.g. block size and
     associativity, are set with command line options (also
     described later).  _d_i_n_e_r_o_I_I_I uses the priority stack method
     of memory hierarchy simulation to increase flexibility and
     improve simulator performance in highly associative caches.
     One can simulate either a unified cache (mixed, data and
     instructions cached together) or separate instruction and
     data caches.  This version of _d_i_n_e_r_o_I_I_I does not permit the
     simultaneous simulation of multiple alternative caches.

     _d_i_n_e_r_o_I_I_I differs from most other cache simulators because
     it supports sub-block placement (also known as sector place-
     ment) in which address tags are still associated with cache
     blocks but data is transferred to and from the cache in
     smaller sub-blocks.  This organization is especially useful
     for on-chip microprocessor caches which have to load data on
     cache misses over a limited number of pins.  In traditional
     cache design, this constraint leads to small blocks.  Unfor-
     tunately, a cache with small block devotes much more on-chip
     RAM to address tags than does one with large blocks.  Sub-
     block placement allows a cache to have small sub-blocks for
     fast data transfer and large blocks to associate with
     address tags for efficient use of on-chip RAM.

     Trace-driven simulation is frequently used to evaluating
     memory hierarchy performance.  These simulations are repeat-
     able and allow cache design parameters to be varied so that
     effects can be isolated.  They are cheaper than hardware
     monitoring and do not require access to or the existence of
     the machine being studied.  Simulation results can be
     obtained in many situations where analytic model solutions
     are intractable without questionable simplifying assump-
     tions.  Further, there does not currently exist any gen-
     erally accepted model for program behavior, let alone one
     that is suitable for cache evaluation; workloads in trace-
     driven simulation are represented by samples of real work-
     loads and contain complex embedded correlations that syn-
     thetic workloads often lack.  Lastly, a trace-driven



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     simulation is guaranteed to be representative of at least
     one program in execution.

     _d_i_n_e_r_o_I_I_I reads trace input in _d_i_n format from _s_t_d_i_n.  A _d_i_n
     record is two-tuple _l_a_b_e_l _a_d_d_r_e_s_s.  Each line of the trace
     file must contain one _d_i_n record.  The rest of the line is
     ignored so that comments can be included in the trace file.

     The _l_a_b_e_l gives the access type of a reference.

         0  read data.
         1  write data.
         2  instruction fetch.
         3  escape record (treated as unknown access type).
         4  escape record (causes cache flush).

     The _a_d_d_r_e_s_s is a hexadecimal byte-address between 0 and
     ffffffff inclusively.  By default, hex addresses should NOT
     be preceded by ``0x'', should be constructed with lower-case
     digits (0123456789abcdef, NOT ABCDEF) and no error checking
     is done.  Programmers can re-enable error-checking by com-
     menting out ``#define FAST_BUT_DANGEROUS_INPUT'' in file
     global.h.

     Cache parameters are set by command line options.  Parame-
     ters _b_l_o_c_k__s_i_z_e and either _u_n_i_f_i_e_d__c_a_c_h_e__s_i_z_e or both
     _d_a_t_a__c_a_c_h_e__s_i_z_e and _i_n_s_t_r_u_c_t_i_o_n__c_a_c_h_e__s_i_z_e must be speci-
     fied.  Other parameters are optional.  The suffixes _K, _M and
     _G multiply numbers by 1024, 1024^2 and 1024^3, respectively.

     The following command line options are available:

     ----bbbb _b_l_o_c_k__s_i_z_e
          sets the cache block size in bytes.  Must be explicitly
          set (e.g. -b16).

     ----uuuu _u_n_i_f_i_e_d__c_a_c_h_e__s_i_z_e
          sets the unified cache size in bytes (e.g., -u16K).  A
          unified cache, also called a mixed cache, caches both
          data and instructions.  If _u_n_i_f_i_e_d__c_a_c_h_e__s_i_z_e is posi-
          tive, both _i_n_s_t_r_u_c_t_i_o_n__c_a_c_h_e__s_i_z_e and _d_a_t_a__c_a_c_h_e__s_i_z_e
          must be zero.  If zero, implying separate instruction
          and data caches will be simulated, both
          _i_n_s_t_r_u_c_t_i_o_n__c_a_c_h_e__s_i_z_e and _d_a_t_a__c_a_c_h_e__s_i_z_e must be set
          to positive values.  Defaults to 0.

     ----iiii _i_n_s_t_r_u_c_t_i_o_n__c_a_c_h_e__s_i_z_e
          sets the instruction cache size in bytes (e.g.
          -i16384).  Defaults to 0 indicating a unified cache
          simulation.  If positive, the _d_a_t_a__c_a_c_h_e__s_i_z_e must be
          positive as well.




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     ----dddd _d_a_t_a__c_a_c_h_e__s_i_z_e
          sets the data cache size in bytes (e.g. -d1M).
          Defaults to 0 indicating a unified cache simulation.
          If positive, the _i_n_s_t_r_u_c_t_i_o_n__c_a_c_h_e__s_i_z_e must be posi-
          tive as well.

     ----SSSS _s_u_b_b_l_o_c_k__s_i_z_e
          sets the cache sub-block size in bytes.  Defaults to 0
          indicating that sub-block placement is not being used
          (i.e. -S0).

     ----aaaa _a_s_s_o_c_i_a_t_i_v_i_t_y
          sets the cache associativity.  A direct-mapped cache
          has associativity 1.  A two-way set-associative cache
          has associativity 2.  A fully associative cache has
          associativity _d_a_t_a__c_a_c_h_e__s_i_z_e/_b_l_o_c_k__s_i_z_e.  Defaults to
          direct-mapped placement (i.e. -a1).

     ----rrrr _r_e_p_l_a_c_e_m_e_n_t__p_o_l_i_c_y
          sets the cache replacement policy.  Valid replacement
          policies are _l (LRU), _f (FIFO), and _r (RANDOM).
          Defaults to LRU (i.e. -rl).

     ----ffff _f_e_t_c_h__p_o_l_i_c_y
          sets the cache fetch policy.  Demand-fetch (_d), which
          fetches blocks that are needed to service a cache
          reference, is the most common fetch policy.  All other
          fetch policies are methods of prefetching.  Prefetching
          is never done after writes.  The prefetch target is
          determined by the ----pppp option and whether sub-block
          placement is enabled.

              d  demand-fetch which never prefetches.
              a  always-prefetch which prefetches after every
          demand reference.
              m  miss-prefetch which prefetches after every
          demand miss.
              t  tagged-prefetch which prefetches after the first
          demand miss to a (sub)-block.  The next two prefetch
          options work only with sub-block placement.
              l  load-forward-prefetch (sub-block placement only)
          works like prefetch-always within a block, but it will
          not attempt to prefetch sub-blocks in other blocks.
              S  sub-block-prefetch (sub-block placement only)
          works like prefetch-always within a block except when
          references near the end of a block.  At this point
          sub-block-prefetches references will wrap around within
          the current block.

          Defaults to demand-fetch (i.e. -fd).

     ----pppp _p_r_e_f_e_t_c_h__d_i_s_t_a_n_c_e



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          sets the prefetch distance in sub-blocks if sub-block
          placement is enabled or in blocks if it is not.  A
          prefetch_distance of 1 means that the next sequential
          (sub)-block is the potential target of a prefetch.
          Defaults to 1 (i.e. -p1).

     ----PPPP _a_b_o_r_t__p_r_e_f_e_t_c_h__p_e_r_c_e_n_t
          sets the percentage of prefetches that are aborted.
          This can be used to examine the effects of data refer-
          ences blocking prefetch references from reaching a
          shared cache.  Defaults to no prefetches aborted (i.e.
          -P0).

     ----wwww _w_r_i_t_e__p_o_l_i_c_y
          selects one of two the cache write policies.  Write-
          through (_w) updates main memory on all writes.  Copy-
          back (_c) updates main memory only when a dirty block is
          replaced or the cache is flushed.  Defaults to copy-
          back (i.e. -wc)

     ----AAAA _w_r_i_t_e__a_l_l_o_c_a_t_i_o_n__p_o_l_i_c_y
          selects whether a (sub)-block is loaded on a write
          reference.  Write-allocate (_w) causes (sub)-blocks to
          be loaded on all references that miss.  Non-write-
          allocate (_n) causes (sub)-blocks to be loaded only on
          non-write references that miss.  Defaults to write-
          allocate (i.e. -Aw).

     ----DDDD _d_e_b_u_g__f_l_a_g
          used by implementor to debug simulator.  A debug_flag
          of _0 disables debugging; _1 prints the priority stacks
          after every reference;  and _2 prints the priority
          stacks and performance metrics after every reference.
          Debugging information may be useful to the user to
          understand the precise meaning  of all cache parameter
          settings.  Defaults to no-debug (i.e. -D0).

     ----oooo _o_u_t_p_u_t__s_t_y_l_e
          sets the output style.  Terse-output (_0) prints results
          only at the end of the simulation run.  Verbose-output
          (_1) prints results at half-million reference increments
          and at the end of the simulation run.  Bus-output (_2)
          prints an output record for every memory bus transfer.
          Bus_and_snoop-output (_3) prints an output record for
          every memory bus transfer and clean sub-block that is
          replaced.  Defaults to terse-output (i.e. -o0).  For
          bus-output, each bus record is a six-tuple:

          _B_U_S_2 are four literal characters to start bus record
          _a_c_c_e_s_s is the access type ( _r for a bus-read, _w for a
          bus-write, _p for a bus-prefetch, _s for snoop activity
          (output style 3 only).



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          _s_i_z_e is the transfer size in bytes
          _a_d_d_r_e_s_s is a hexadecimal byte-address between 0 and
          ffffffff inclusively
          _r_e_f_e_r_e_n_c_e__c_o_u_n_t is the number of demand references
          since the last bus transfer
          _i_n_s_t_r_u_c_t_i_o_n__c_o_u_n_t is the number of demand instruction
          fetches since the last bus transfer

     ----ZZZZ _s_k_i_p__c_o_u_n_t
          sets the number of trace references to be skipped
          before beginning cache simulation.  Defaults to none
          (i.e. -Z0).

     ----zzzz _m_a_x_i_m_u_m__c_o_u_n_t
          sets the maximum number of trace references to be pro-
          cessed after skipping the trace references specified by
          _s_k_i_p__c_o_u_n_t . Note, references generated by the simula-
          tor not read from the trace (e.g. prefetch references)
          are not included in this count.  Defaults to 10 million
          (i.e. -z10000000).

     ----QQQQ _f_l_u_s_h__c_o_u_n_t
          sets the number of references between cache flushes.
          Can be used to crudely simulate multiprogramming.
          Defaults to no flushing (i.e. -Q0).

FFFFIIIILLLLEEEESSSS
     _d_o_c._h contains additional programmer documentation.

SSSSEEEEEEEE AAAALLLLSSSSOOOO
     Mark D. Hill, _T_e_s_t _D_r_i_v_i_n_g _Y_o_u_r _N_e_x_t _C_a_c_h_e, _M_a_g_a_z_i_n_e _o_f
     _I_n_t_e_l_l_i_g_e_n_t _P_e_r_s_o_n_a_l _S_y_s_t_e_m_s (_M_I_P_S), August 1989, pp. 84-92.

     Mark D. Hill and Alan Jay Smith, _E_x_p_e_r_i_m_e_n_t_a_l _E_v_a_l_u_a_t_i_o_n _o_f
     _O_n-_C_h_i_p _M_i_c_r_o_p_r_o_c_e_s_s_o_r _C_a_c_h_e _M_e_m_o_r_i_e_s, _P_r_o_c. _E_l_e_v_e_n_t_h _I_n_t_e_r_-
     _n_a_t_i_o_n_a_l _S_y_m_p_o_s_i_u_m _o_n _C_o_m_p_u_t_e_r _A_r_c_h_i_t_e_c_t_u_r_e, June 1984, Ann
     Arbor, MI, pp. 158-174.

     Alan Jay Smith, _C_a_c_h_e _M_e_m_o_r_i_e_s, _C_o_m_p_u_t_i_n_g _S_u_r_v_e_y_s, 14-3,
     September 1982, pp. 473-530.

BBBBUUUUGGGGSSSS
     Many things break when the number of addresses simulated
     approaches the maximum 32-bit integer (4,294,967,295).

AAAAUUUUTTTTHHHHOOOORRRR
     Mark D. Hill
     Computer Sciences Dept.
     1210 West Dayton St.
     Univ. of Wisconsin
     Madison, WI 53706




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     markhill@cs.wisc.edu






















































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