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UPC: Parallel Computer Architecture

Spring 2003

Instructor Mark D. Hill

URL: http://www.cs.wisc.edu/~markhill/upc/

Last updated on Tuesday, 06-Jan-2004 17:23:58 CST

Goal

The goal of this Ph.D. course is to provide a computer architect's view of parallel computer hardware, with an emphasis on shared-memory systems. The course is an accelerated version of CS/ECE 757 that the instructor teaches at the University of Wisconsin-Madison.

The course will be taught via reading a dozen papers and thirty hours of lecture and discussion. Students by evaluated via class participation and two examinations. The course assumes that students are familiar with single-processor computer architecture at the level taught in Hennessy and Patterson's A Quantitative Approach.

Information registered students should (and other attendees could) provide to help me by Wednesday, 30 April.

Instructor: Mark D. Hill

Office:         D6 212
Email           Email Address of Mark Hill

Lecture

Time:           10:00 - 13:00 Monday, Wednesday, and Friday
		during four weeks beginning April 28.
Place:          D6-004 & other rooms (see Outline)

Approximate Lecture Notes

These notes are (or will be) abbreviated from CS/ECE 757 Notes.
(Please, print close to when the topics are covered, since I may revise them.)

Examinations

There will be two in-class exams at the middle and end of lectures.

Grading

Approximate Outline

Lecture Date Room Topic
1Monday 28/04D6-S004Introduction
2Wednesday 30/04D6-S103Parallel Programming
--Friday 02/05D6-S103class canceled
3Monday 05/05C6-E101Symmetric Multiprocessors 1
4Wednesday 07/05D6-S103Symmetric Multiprocessors 2
5Friday 09/05D6-S103Catch-up/Review
6Monday 12/05C6-E101EXAM1/Scalable Multiprocessors
7Wednesday 14/05C6-E101Distributed Shared Memory 1
8Friday 16/05D6-S103Distributed Shared Memory 2
9Monday 19/05D6-S103Catch-up/Review
10Wednesday 21/05D6-S103EXAM2/Future Directions
--Friday 23/05D6-S103reserved if needed

Required Readings

This list may be revised. Paper downloads are restricted to .upc.es. Some papers and scanned in and greater than 1MB.

Introduction: Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Introduction to Chapter 9 "Multiprocessors and Multicomputers," from Readings in Computer Architecture, Morgan Kaufmann, 2000 (pdf).

Parallel Programming: Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta, The SPLASH-2 Programs: Characterization and Methodological Considerations, Proc. International Symposium on Computer Architecture, June 1995 (pdf).

Parallel Programming: Luiz Andre Barroso, Kourosh Gharachorloo, and Edward Bugnion, Memory System Characterization of Commercial Workloads, Proc. International Symposium on Computer Architecture, June 1998 (pdf).

Symmetric Multiprocessors 1: Paul Sweazey and Alan Jay Smith, A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus, Proc. Thirteenth International Symposium on Computer Architecture, June 1986 (pdf).

Symmetric Multiprocessors 1: Leslie Lamport, How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs, IEEE Tran. on Computers, September 1979, pp. 690-691 (not online).

Symmetric Multiprocessors 2: Alan Charlesworth, Starfire: Extending the SMP Envelope, IEEE Micro, January/February 1998, pp. 39-49 (pdf) .

Scalable Multiprocessors: Steven L. Scott, Synchronization and Communication in the T3E Multiprocessor, Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems, pages 26-36, October 1996 (pdf).

Distributed Shared Memory 1: James Laudon and Daniel Lenoski The SGI Origin: A ccNUMA Highly Scalable Server, In Proceedings of International Symposium on Computer Architecture, pages 241-251, June 1997 (pdf).

Distributed Shared Memory 1: Sarita V. Adve and Kourosh Gharachorloo, Shared Memory Consistency Models: A Tutorial, IEEE Computer, 29(12):66-76, December 1996 (pdf).

Distributed Shared Memory 2: Cristiana Amza, et al., TreadMarks: Shared Memory Computing on Networks of Workstation, IEEE Computer, 29(2):18-28, February 1996 (pdf).

Distributed Shared Memory 2: Erik Hagersten and Michael Koster, WildFire: A Scalable Path for SMPs, Proc. High-Performance Computer Architecture, January 1999 (pdf).

Future Trends: Luiz Andre Barroso, et al., Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing, Proc. International Symposium on Computer Architecture, June 2000, pp. 282-293 (pdf).

Future Trends: Milo M. K. Martin, Mark D. Hill, and David A. Wood, Token Coherence: Decoupling Performance and Correctness, International Symposium on Computer Architecture, June 2003 (pdf).

Optional Reference Material

  David Culler and J. P. Singh with Anoop Gupta
  Parallel Computer Architecture: A Hardware/Software Approach
  Morgan Kaufmann Publishers, 1998.
  See book's home page for auxiliary information or to order.

  Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi
  Readings in Computer Architecture
  Morgan Kaufmann Publishers, 2000.
  See book's home page for auxiliary information or to order.

  Mark D. Hill and Min Xu
  CS/ECE 757 Reading List
  Spring 2002

Miscellanea



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