1. Peter Hsu, TX79: A MIPS-Compatible Synthesizable Core with Multimedia Vector Extensions, Proceedings of Microprocessor Forum, October 2000.
  2. Peter Y.-T. Hsu,Designing the TFP Microprocessor, IEEE Micro, Vol. 14, No. 2, April 1994.
  3. Peter Y.-T. Hsu, Silicon Graphics TFP Micro-Supercomputer Chipset, Proceedings of the Hot Chips V Conference, 1994.
  4. Ikumi, et. al., A 300MIPS, 300MFLOPS Four-Issue CMOS Superscalar Microprocessor, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), February 1994.
  5. P. Y.-T. Hsu, B. R. Rau and K. J. M. Moriarty, Applications Development on the Very Long Instruction Word Cydra-5, International Journal of Supercomputer Applications, Vol. 3, No. 3, Fall 1989.
    6. James C. Dehnert, Peter Y.-T. Hsu and Joseph P. Bratt, Overlapped Loop Support in the Cydra 5, Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-III), April 1988, Boston, Massachusetts.
  6. Peter Y.-T. Hsu and Edward S. Davidson, Highly Concurrent Scalar Processing, Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA-13)
  7. Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson and Jacob A. Abraham, TIDBITS: Speedup Via Time-Delayed Bit-Slicing in ALU Design for VLSI Technology, Proceedings of the 12th Annual International Symposium on Computer Architecture (ISCA-12)