Mark D. Hill

Professor of Computer Sciences and Electrical and Computer Engineering, and Romnes Fellow

Computer Sciences Department
University of Wisconsin
1210 W. Dayton St.
Madison, WI 53706-1685

telephone: (608) 262-1204
fax: (608) 262-9777
email: markhill@cs.wisc.edu
http://www.cs.wisc.edu/~markhill/

Ph.D., University of California, Berkeley, 1987
Interests: Computer architecture, parallel computing, memory systems, performance evaluation

Research Summary

My research targets the memory systems of shared-memory multiprocessors and high-performance uniprocessors. Memory system design is important because it largely determines a computer's sustained performance. My work emphasizes quantitative analysis (often requiring new evaluation techniques) of system-level (not just hardware) performance.

Over the last several years much of my work has been part of the the Wisconsin Wind Tunnel Project with Profs. Larus and Wood. This project has focused on trade-offs for designing cost-effect parallel machines supporting shared memory. The first phase examined Cooperative Shared Memory that simplified shared memory hardware by allowing software to manage data movement. The second phase proposed the more-general Tempest interface that enabled programmers, compilers, and program libraries to implement and use message passing, transparent shared memory, and hybrid combinations of the two.

We are now moving into a third phase which returns to a greater hardware emphasis and seeks to find coherence solutions that gracefully evolve as system size increases. These would allow small systems (e.g., 4-16 processors) to use snooping, large systems to use directories (e.g., 256 or more processors), and intermediate systems to use new hybrids.

Other recent research includes efforts to move network interfaces to coherent memory buses, the application of Lamport's logical clocks to shared-memory verification, and the use of prediction in coherence protocols.

Sample Recent Publications

Making network interfaces less peripheral (with S. Mukherjee), IEEE Computer, 1998.

Lamport clocks: Verifying a directory cache-coherence protocol (with M. Plakal, D. Sorin, and A. Condon), Proceedings of the Symposium on Parallel Algorithms and Architectures, 1998.

Using prediction to accelerate coherence protocols (with S. Mukherjee), Proceedings of the 25th International Symposium on Computer Architecture, 1998.

This page was automatically created December 30, 1998.
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