(2.2.1) Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy

     For rapid cache access

Problems

     synonyms (different virtual addresses > same physical address)

     addr translation anyway required for a miss

     cache coherence bowled.

     I/O addressed physically

     context switch needs invalidation

Write through for the first level (coherence is simplified) and write back for the second level preferred. 

Writes tend to occur in bulk (in procedure calls) > use write buffers (lots needed) > Cache coherence becomes a problem > use write back. 

reverse translation table for detecting synonyms (second level). when v-cache miss > go down > hit > check if syn exists > inv the old one and copy over new virt address

for using virtual addressing : 

     + memory bandwidth to processor

     -  write backs in burst when context switch occurs (paper suggests dirty dirty bit).

for physical : 

     cache coherence simple

     synonyms headache avoided.

     

     says hit rates for combined I & D cache comparable to split.