Bruce Jacob and Trevor Mudge. Virtual Memory on Contemporary Processors, IEEE Micro, vol. 18, no. 4, 1998. IEEE Xplore link |
Classic Memory Management Unit > Translation look-aside buffer (cache of page table entries), an fsm that walks the page table
fully associative TLB > bad timing, set associative popular (power consumption/clock speed)
problem with software controlled > OS is typically written generic, > OS not tuned to hardware on which it operates. unlikely to live up to its potential performance.
MIPS <<<<
OS handles TLB misses. software fills the TLB, OS defines TLB replacement policy.
64 bit > top 2 bits : user, supervisor and kernel spaces. (in 32 bit R2000/R3000 : bit 31 : user/kernel, 30:29 : cached/uncached and mapped/unmapped regions.
virtual address extended with address space identifier (ASID) (6 bit = 64 processes).
TLB filled randomly/OS tells which slot to replace. (TLBWR) / TLBWI : instructions.
N noncacheable, D dirty (writable) V valid, G global (TLB ignores ASID match > shared memory).
ALPHA <<<<
Software managed, split TLB/cache.
Not OS but PALcode (privilege access code). not-most-recently-used policy for replacement.
Address space match (ASID indep match).
Granularity Hint : 2 bits > 8^GH pages = 1 super page.
PowerPC <<<<
inverted page table (scalability : physical page table size limits, not virtual)
paged segmentation : TLBs and page table map an extended virtual address space, not application's effective address space.
segment = 256MB of continuous regions of virtual space.
>> basically things are not continuos. each process has the same 4 GB, but 4x 1GB with pointetrs.
no ASIDs : OS can modify protection on segment registers.
Superpage > block address translation mechanism : BAT takes precedence over TLB when BAT signals hit.
BAT has only OS/User priv distinguish > if context switch happens and no sharing is desired, explicitly flush the BAT.
PA-RISC <<<<
segmentation like PowerPC.
Protection ID : running process compared with access ID : virtual page.
user level access to space registers > processes can change their address space. > additional protection mechanism required.
each page has associated ID protection > 2 processes can share (! all or nothing) parts of their space.
UltraSPARC <<<<
ASIs (ASIDs) > dont identify contexts but identifies data formats and privileges.
IA-32 <<<<
amalgamation of several techniques.
Pentium II
segmented with no explicit ASIDs.
segmentation is just not used in OSs, typically flush the TLB on context switch to provide protection.
Caches are physically indexed and tagged > no flush on context switch
TLB miss : hardware walks the page table (from CR3 : context page table root).
sharing : duplicating mapping information across page tables.
1 byte to 4GB segments : size set by software and can differ for every segment.
segment descriptor : privilege, granularity (size) etc.,
-----
virtual vs physical caches
protection methods (ASICs, segments, multiple IDs)
address-space organization(segmented/fla, page table support, super page support)
virtual cache > data consistency issues managed by OS.
protection mechanism > OS's model of obj allocaiton : allocate and destroy large/small objects,
besteshwar : hardware walked, inverted page table.