Jerry Huck, Dale Morris, Jonathan Ross, Allan Knies, Hans Mulder, Rumi Zahir. Introducing the IA-64 Architecture. IEEE Micro, vol. 20, no. 5, pp. 12-23, Sep./Oct. 2000. IEEE Xplore link |
Intel-HP Itanium architecture
Instr encoding
128 registers => 7 bits to specify 3 reg operands
128 bit bundle : encoding : 3 instr, ^ 7*3 + 5 bit template > start and stop of instr exec in parallel, decode and route the instr
Sequential schematics : compiler knows things commit in order
IA-64 : parallel sch :
ILP : instruction group (safely exec in parallel)
Control flow parallelism :
combine something like (a==0) || (b<=5) || (c!=d) then r8 = 4; into one parallel instr block
used specifically in multiway branch pred
predication
Control Speculation
speculative load > then propogate the possible exception to all depending instr, chk.a the very end to find if speculation is okay or branch to fix-up code
Data Speculation
because of pointers data speculation is pretty difficult
use speculation similar to above : load speculatively, store the address and size in an advanced load status table.
subsequent stores check this table for a possible match, if present then speculation success, else fix-up code.
Register model
First 32 are static, next registers are rotating.
when you enter a procedure, alloc reg locals and outputs. when exit, register rename revert.
when overflow happens, RSE (register stack engine) stores reg to mem and restore can take place.
Software pipelining
loop level parallism
Loop count register, epilog count
rotating registers help, predicates
Virtual memory
core of OS's multitasking and protection mech
because of 64 bit (16 billion GB) non exhaustive hardware reqd
Regions
on context switch, OS only flushes exit region
Protection Keys
page granular control (shared between OS/user kinds)
multiple page sizes