T. Mudge. Power: A first class design constraint. Computer, vol. 34, no. 4, April 2001, pp. 52-57. IEEE Xplore link |
Power equations for CMOS
P = A C V^2 f + A V Ishort + V Ileak
fmax = (V - Vt)^2 / V
Ileak = exp (-Vt/35mV)
reducing voltage has significant effect on power consumption P prop V^2
reducing activiity does as well : clock gating
parallel processing is good if it can be done efficiently > if computation can be split in two and run as two parallel independent tasks => power cut in half, no perf loss!
worry about
peak power
dynamic power
total energy
>> Measure MIPS/W
>> or energy*delay
Tech for reducing
Logic
Clock gating
Half frequency and half swing clocks
async logic
Architecture
Memory systems
buses
gray code
parallel processing and pipelining
OS
Voltage scaling
scheduling
with High MIPS/W
do scheduling such that applications dont complete well before deadline.