Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma: Optimizing pipelines for power and performance. MICRO 2002: 333-344. IEEE Xplore link |
Develop an analytical model to understand power and perf tradeoffs for super scalar pipelines.
contributions
energy models for dynamic and leakage power to capture the scaling of different power components as a function of pipeline depth
analytical perf model that can predict optimal pipeline depth
cycle accurate detailed power-performance simulation (with sensitivity analysis of optimal pipeline depth).
someother paper : 7.7 FO4 = optimal pipeline depth for SPEC2000, 5.5 FO4 for traditional and Java/C++. (+latch insertion of 3 FO4).
P is total power of pipe i > energy delay product ED = P/G^2. optimal d(BIPS)^y/W)/ds = 0.
Hold power primarily consists of power dissipated in latches, local clock buffers, global clock network, data independent fraction of arrays.
switching power : combo logic, data-dependent array power dissipation, switching factors.
Dynamic power = CV2f*(a+b)*CFG a = functionality, b = glitching factor.
leakage power = VIleak
Latch Scale = latch ratio * (Fo4base design/FO4 logic)^LGF
fact adj hold power diss = hold pwr to total power, LFG = growth of latch count dur to logic shape func.typically > 1
Dynamic power increases more than quadratically with increased pipeline depth.
Metrics with Less emphasis on performance (BIPS/W, BIPS^2/W : shallower pipelines, deeper pipelines for more pef). Optimal for BITS3/W is 19-24.
Using BIPS3/W :
high LGF favor shallower pipelines, lower values of Latch Ratio favor deeper pipelines, use of low power latches favors shallower pipelines, higher values of Glitch factor favors deeper pipelines and high leakage > deeper pipelines.
depend on workload characteristics.