Dan Ernst, et al., A Low-Power Pipeline Based on Circuit-Level Timing Speculation, MICRO 2003. IEEE Xplore link |
Physical Design paper MICRO 03
A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Background
Dynamic Voltage scaling
Critical supply voltage < V
OCV to account for process variations
or delay chains (inverters) to measure it after chip manufacturing
Razor
Shadow latch clocked by a delayed clock, guaranteed to hold correct value
compare actual ff vs shadow for error
combination of architectural and circuit level dagajis
recovery > one cycle penalty.
Do something like instruction stall/clock gating to account for that one cycle
Only used in PVT corner affected flops replaced by Razor
metastability handling > takes 2 cycles => flush pipeline required.
Recovery methods
Clock gating
Counter flow pipelining
Proportional control system
Voltage scaling based on measured (sampled) error rates