D. Burger et al. Scaling to the End of Silicon with EDGE Architectures. IEEE Computer 2004. Volume: 37, Issue: 7. ACM DL Link |
what drove comp arch
1970 : Memory was expensive
1980 : no of devices that could fit in chip
now : MHz wall
4 major emerging tech characteristics
Pipeline depth limits > fine-grained concurrency mechanisms to improve performance
Power
on-chip communication dominant execution
polymorphism (multi function)
EDGE : Explicit data flow graph execution
Groups of instructions > hyperblock that can be run in parallel
Architecture + compile balance :
RISC : Arch has to look for (reconstruct) dependencies (dynamic placement, dynamic issue)
VLIW : very difficult for compiler. (static p, static i)
EDGE : static placement, dynamic issue
Compiler's jobs
>> Large hyperblock formation
>> Predicated execution (just create a dependency on the first of the instructions, dependency following will auto block rest)
>> Generating legal hyperblocks (device constraints)
>> Physical placement
Parallelism
Data level P is kind of obvious
TLP : 4 threads > evenly distribute exec blocks to threads