Dally and Towles, "Route packets, not wires: on-chip interconnection networks" , DAC 2001. IEEE Xplore link, http://cva.stanford.edu/publications/2001/onchip_dac01.pdf |
Use soemthing like PCI on chip. all modules talk to each other thru a standardized interface, network routes packets to destinations.
Suggested network
input port : 256 bit data + control field.
Type (Flow control digit or FLIT) : 2 bits : new packet (head), tail, middle or idle.
Size (4 bits) log of data size.
Virtual Channel (8 bits) bit mask.
Route (16 bits) : encoded as 2 bits for each hop till the destination. (NEWS).
Ready : a signal from the network back to the client indicating network is ready.
Output ports
Registers : ex : time-slot reserv for certain classes of traffic.
Higher level protocol can be piggy backed on this.
Router : 5 input controller (NEWS + self), 5 output contrllers.
Fault tolerance : can find out which routers are crappy. and adapt accordingly.
Pre-scheduled and dynamic traffic. (using virtual channels)
Differences between intra and interchip networks :
1) lots of pins available. => wide flits possible. folded torus topology is employed. (2x wire demand, 2x bandwidth demand).
2) reduced buffer storage requirements.
3) Specialized transievers possible.
Area overhead exists (for routers) but
1) predicatable electrical parameters => tweakable
2) reuse with universal interface
3) reuse to network
4) network => duty factor of wires increased.
Structure performance and modularity adv if you replace top-level wiritng with on-chip interconnects.