Ravi Rajwar's Homepage
I have graduated from the Computer Sciences Department
at the University of Wisconsin-Madison.
My advisor was Jim
Goodman , a professor in the
architecture group at the University of Wisconsin-Madison.
I received a Bachelors degree in
Computer Science and Engineering (With Honors) from the Indian Institute of Technology, Roorkee,
India, in 1994, a Masters degree in Computer Sciences from
the University of Wisconsin-Madison in 1998, and a Ph.D degree
in Computer Sciences from the University of Wisconsin-Madison in
My linkedin profile has some additional information.
Any computing system. I find many things
interesting. I dabble in microarchitecture, multiprocessing, threaded architectures,
future cache coherence protocols, memory system design, simulation
techniques, hardware verification techniques, parallelism, parallel software, memory ordering, and architecture/compiler
Fun fact - my Erdös Number is 3.
ACM SIGARCH Maurice Wilkes Award (2014)
ACM SIGARCH/SIGPLAN/SIGOPS ASPLOS Most Influential Paper Award (2013)
IEEE MICRO Top Picks in Computer Architecture Selections (2008,2006,2004,2003,2003)
ACM SIGMICRO Best Paper Award (Dec 2001)
Outstanding Graduate Research Award (Computer Sciences Department, May 2002)
WARF Graduate School Fellow (1996-97)
Frank Roger Bacon Fellow (1996-97)
Haswell: A Family of IA 22 nm Processors
Nasser Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, Mark Neidengard, Anant Deval, Ashish Khanna, Nasirul Chowdhury, Ravi Rajwar, Timothy M. Wilson, and Rajesh Kumar
IEEE Journal of Solid State Circuits, Vol. 50, No. 1, January 2015.
Haswell: The Fourth Generation Intel Core Processor
Per Hammarlund, Alberto J Martinez, Atiq A Bajwa, David L Hill, Erik Hallnor, Hong Jiang, Martin Dixon, Michael Derr, Mikal Hunsaker, Rajesh Kumar, Randy B Osborne, Ravi Rajwar, Ronak Singhal, Renold D'Sa, Robert Chappell, Shiv Kaushik, Srinivas Chennupaty, Stephan Jourdan, Steve Gunther, Tom Piazza, and Ted Burton.
IEEE Micro, Vol. 34, Issue 2, April 2014
Transactional Memory and Synchronization: A Hardware Perspective
Seventh Winter School on Hot Topics in Distributed Computing, La Plagne, France, HTDC 2014, March 2014
Adventures in Parallel Dimensions
27th International Symposium on Distributed Computing, October 2013
Transactional Memory and Synchronization
Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiuggi, Italy, ACACES'12, July 2012
In Search of Parallel Dimensions
24th ACM Symposium on Parallelism in Algorithms and Architectures, Jun 2012
Building Functionally Correct Systems in the Multi-Core Era
Exploiting Concurrency Efficiently and Correctly (CAV 2008), Jul 2008
Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, and Craig Zilles
IEEE Micro Special Issue (Top Picks in Computer Architecture) January 2008.
Implications of False Conflict Rate Trends for Robust Software Transactional Memory
Craig Zilles and Ravi Rajwar
10th IEEE International Symposium on Workload Characterizatioan (IISWC), 2007.
Scalable Load and Store Processing in Latency Tolerant Processors
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, and Konrad Lai
IEEE Micro Special Issue (Top Picks in Computer Architecture) January 2006.
The Atomic Manifesto: a Story in Four Quarks
Cliff Jones, David Lomet, Alexander Romanovsky, Gerhard Weikum, Alan Fekete, Marie-Claude Gaudel, Henry F. Korth, Rogerio de Lemos, Eliot Moss, Ravi Rajwar, Krithi Ramamritham, Brian Randell, and Luis Rodrigues
SIGMOD Record, March 2005 / SIGOPS Operating Systems Review, April 2005
Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, and Mike Upton
IEEE Micro Special Issue (Top Picks in Computer Architecture) November/December 2004.
Continual Flow Pipelines
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi and Mike Upton
11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004.
Transactional Lock-Free Execution of Lock-Based Programs (or pdf)
Ravi Rajwar and James R. Goodman
10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002.
(Received the 2013 ACM SIGARCH/SIGPLAN/SIGOPS ASPLOS Most Influential Paper Award)
Characterizing a Java Implementation of TPC-W
Todd Bezenek, Trey Cain, Ross Dickson, Tim Heil, Milo Martin, Collin McCurdy, Ravi Rajwar, Eric Weglarz, Craig Zilles, and Mikko Lipasti
Third Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), January 2000.
An excellent talk by Richard Hamming -- "You and Your Research"
How to give a talk... by Mark Hill -- Oral Presentation Advice
How to review papers... by Alan Jay Smith -- The Task of the Referee
How not to write papers... by Jonathan Shewchuk -- Three Sins of Authors in Computer Science and Math
How not to plan a career... by David Patterson -- How to Have a Bad Academic Career
Multiprocessor publication trends... by Mark Hill and Ravi Rajwar -- Multiprocessor Papers in ISCA
The first workshop on Transactional Memory...Workshop on Transactional Systems April 2005.