40, North Orchard Street



Visa Status – F-1

Phone  (cell)  (608)335-0381

E-mail ram@cs.wisc.edu

URL : http://www.cs.wisc.edu/~ram


Ramanathan Palaniappan



Systems related opportunity dealing with product design and development.



1. Aug 2004 –  May 2005         University of WisconsinMadison

Madison, WI

M.S. (Computer Sciences )

§     CGPA : 4.0/4.0


Fall 2004:      Advanced Computer Architecture (A)

                    Advanced Databases (A)


Spring 2005:  Advanced Operating systems (A)

                    Advanced Computer Networks  (A)

2. Aug 2000 – May 2004      College of Engineering, Guindy, Anna University Chennai, India

B.E. (Computer Science & Engineering )

§     CGPA : 9.516/10.0

§     Class Rank: 2/120

 Significant Courses( @Anna) :


Advanced Java Programming, Databases, Digital Systems, Operating Systems, Microprocessors, Computer Architecture, Computer Networks, Network Security, Compilers, Artificial Intelligence.                                                                      

Professional experience

1.  June 2005 – Aug 2005 Amazon.com, Seattle, WA.

     SDE intern in the Buying tools/Retail systems group.

2. Aug 2004 – May 2005 Computer Sciences Dept., UW-Madison

    Madison, WI.


Teaching Assistant

§     CS302 – Consultant for Java Programming

§     CS368 – C++ Programming


Ramanathan Palaniappan, Ramkumar Jayaseelan, Vikram Chandiramani, Vimal Kumar Selvam, “Adaptive Binomial Congestion Control Algorithm based on the Loss Rate” appeared in WSEAS Transactions on Communications (Issue 4, Volume 2, October 2003, pp 527-532).



Graduate Projects:


# Energy Awareness in the Linux Virtual Memory Manager (Spring 2005)


Latest trends in memory technology like RAMBUS allow memory modules to operate in low power mode when there is less activity on that module. In this project, we have developed a kernel level mechanism called “Ballooning in the Operating System” that can predict the access pattern to these memory modules and suitably make decisions which conserve power. This becomes really important for mobile devices like laptops and cell phones where power is a scarce resource. The memory modules were not actually powered down but instead, the power down effect was emulated within the kernel using page migration and a new technique called the “Invisible Buddy”.


# Time Synchronization using NTP- GPS vs. TSC ( Spring 2005 )


NTP servers synchronized using GPS clocks have been the standard for synchronizing clocks in the internet. Recent research has focused on more cost effective solutions like TSC (Time Stamp Counter) clocks which make use of the TSC register available in the x86 machines. This project involved setting up a NTP Stratum-1 server in the WAIL (Wisconsin Advanced Internet Laboratory) which is synchronized by a GPS receiver and empirically evaluating this clock with the TSC based clock.


# Performance Analysis of Microeconomic Algorithms to Distributed Query Processing. ( Fall 2004 )

Many Microeconomic approaches have been proposed to the problem of load balancing in distributed systems. Here we explore two such approaches, viz, one based on the Mariposa model and the other one, based on the Ferguson's approach. We obtained interesting insights into the performance of these two algorithms. It was found that the Ferguson's model performed better load balancing when compared to the Mariposa model. The implementation was done in JAVA.


# A Study of Mispredicted Branches Dependent on Load Misses in Continual Flow Pipelines. ( Fall 2004 )

Long Memory Latencies is the primary problem confounding computer architects right now. CFP is one of the proposed solutions to this problem. We implemented CFP in simple scalar and explored how Mispredicted Branches dependent on Load Misses affect CFP’s performance. We also analyzed the impact of instruction fetch mechanism on CFP's performance.


Undergraduate Projects:

# Implementation of the Datagram Congestion Control Protocol (DCCP).

DCCP is a transport layer protocol that is suited to multimedia and streaming applications. It provides an abstract framework within which users can embed custom congestion control algorithms based on their needs. We developed a new congestion control algorithm based on the class of Binomial congestion Control Algorithms and integrated it within the DCCP framework. The entire protocol was implemented in ns2.


# Implementation of an Indirect Branch Prediction Technique in Simple Scalar.

A branch prediction technique for indirect branches based on an "XOR" scheme was implemented in simple scalar. We got an improvement of ~3% over the conventional Branch Target Buffer Technique.


# Designed a Compiler for a subset of the ICON Language.

Lex was used to construct the Lexical Analyzer while Yacc was used to build the Syntax Directed Translator. The Target Language was 8086 assembly.


# Object Oriented Design for a website using IBM-Rational Rose.

The complete design of the website was done in UML (using IBM Rational Rose) and the final implementation was done in Java.


# Simulated Main Memory and Cache Access in VHDL.


# Designed a Digital Stop Clock in Digital Systems Course.  ( Hardware Project )


# Developed a Client Server Application using 8086 assembly.

Computer Skills

C, C++, Java, VHDL, HTML, Java Script, Windows Applications, 8086 assembly.

Lex, Yacc, Perl, Tcl/Tk, SQL, Pl/Sql.

Windows 98/2000/NT, Linux, UNIX.


Awards received

ARVIND MEHTA MEMORIAL PRIZE - University Topper in Mathematics during Freshman Year (Anna University).

State Rank 21 in Tamil Nadu Professional Courses Entrance Examination (conducted by Anna University) – attended by 0.1 million students.

Professional memberships


Executive Member – Student ACM Chapter, Anna University, 2003-2004.                 


Ramanathan Palaniappan