Shubhendu S. Mukherjee (Shubu)Graduate Research AssistantComputer Sciences Department University of Wisconsin - Madison. 1210 West Dayton Street Madison, WI 53706-1685 USA Email: shubu@cs.wisc.edu Phone: (608) 262-5083 Fax: (608) 262-9777 |
| Architecture | CFP (NI Special Issue) | Education & Research | Ballroom Dancing | Etc. |
Advisor: Mark D. Hill
Research Project: Wisconsin Wind Tunnel
Curriculum Vitae
Publications (Network Interfaces, Shared Memory, & Simulation)
Software (Wisconsin Architecture Research Tool Set)
Talks
Wisconsin Computer Architects
World-Wide Computer Architects
Morph between Dionisios and myself
(Courtesy: Steve Seitz)
Other Personal Interests/Hobbies
Some random (but interesting) links
Ph.D
University of Wisconsin-Madison,
(defended on Dec. 17, 1997)
M.S.
University of Wisconsin-Madison
, Sep 1992 - Dec 1993
B.Tech.
Indian Institute of Technology, Kanpur,
India, Aug 1987 - May 1991
My dissertation targeted primarily network interface (NI) devices for message-passing parallel computers. Parallel computers are important because they solve our large scientific and engineering problems. Currently, the least expensive way to build a parallel computer is to connect multiple commodity workstations with a custom or (preferably) commodity high-performance network. Unfortunately, the NI that connects a network to a workstation presents a major bottleneck to low-latency, fine-grain communication that frequently arises in many parallel applications.
My dissertation proposed novel mechanisms to alleviate this NI bottleneck for message-passing parallel computers. First, I proposed a key design principle: treat processor access to an NI as a memory access, and not as a disk interface access. Traditional workstations treat processor access to an NI as a disk I/O operation, even though such accesses involve primarily reading and writing NI memory. For example, NIs are often accessed via an operating system call and NI memory is marked uncacheable. In contrast, treating a processor's access to an NI as a memory access allows modern microprocessors to improve the latency of communication through common memory access optimization techniques (e.g. traditional caches, out-of-order accesses, and speculation).
Second, I proposed and evaluated a novel class of NIs called Coherent Network Interfaces (CNIs). CNIs are an embodiment of my proposed design principle. Unlike conventional NIs, CNIs interact with the memory system of a workstation using coherent, cacheable memory operations. My detailed simulation study shows that the most aggressive CNI outperforms several alternate NI design proposals.
Besides network interfaces, I have worked extensively on cache-coherent, shared-memory parallel computers. Specifically, I have designed a highly accurate coherence protocol message predictor called Cosmos. Cosmos allows a coherence protocol to execute protocol actions and send protocol messages speculatively and thereby reduce latencies incurred by the protocol.
Additionally, I have been an active researcher in the Wisconsin Wind Tunnel (WWT) project (co-led by Mark Hill, James Larus, and David Wood). WWT primarily focussed on cost-effective and high-performance shared-memory parallel computers. As a member of the project I have participated in many aspects of WWT's research, such as the design and development of the Cooperative Shared Memory paradigm, the Tempest parallel programming interface, the Blizzard software shared-memory system, the Dir1SW+ cache coherence protocol, and the Wisconsin Wind Tunnel parallel simulator.
A recent EE Times article reviewed my Hot Interconnects V talk. This article pointed out one of the key conclusions of my thesis: Treat network interface access as memory access, and not as a disk access. Click here for the EE Times article.
Together with Andrew Chien and Mark Hill, I am guest editing a special issue of IEEE Computer on "Design Challenges for High-Performance Network Interfaces". Click here for the call for papers.
My other research contributions are in uniprocessor cache simulation techniques (JSS94), parallel multiprocessor simulation techniques ( Wisconsin Wind Tunnel Tutorial, Wisconsin Wind Tunnel II), distributed shared-memory (Mechanisms, ISCA93, On Commodity SMP workstations, Technical Report), and hardware and software coherence protocols (ISCA93, ICS94, and PPoPP95). Click here for a list of my publications.
Recently, I also wrote two other articles. The first one is titled, "What Should Graduate Students Know Before Joining a Large Computer Architecture Project?". This article summarizes my opinions on pros and cons of large computer architecture research projects in academia. This article appears in Computer Architecture News (CAN), March 1997. I believe my observations apply to large projects in other areas of Computer Science as well, even though this article focuses specifically on computer architecture.
The second article is short humor piece titled, How to Make Computer Programs Run Slower?".
Indian Institute of Technology, Kanpur (IITK)
Indian Colleges/Institutes/Universitites
South Point High School
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