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Homework 4 // Due at lecture Wed, Oct 12
Primary contact for this homework: Rebecca Lam [rjlam@cs.wisc.edu]
You must do this homework in groups of two. Please write the full name and the student id of each member on every pages and staple multiple pages together. Only turn in ONE copy of homework per group.
Problem 1 (4 points)
Implement a full adder with a 3to8 decoder and two multiinput OR gates. Use the table of Figure 3.14 on p.62 of the textbook.
Problem 2 (4 points)
 Implement a 2input NOR gate using one 2to1 mux and one NOT gate
For the above we can also connect input1 to 1 and B to SEL. The following is also a valid answer.
 Implement a 2input NOR gate using one 4to1 mux
Problem 3 (6 points)
Given that a certain machine has a clock frequency of 40MHz and takes 6 cycles to execute an instruction, find the following:
 Clock cycle period
Clock cycle time = 1 / Clock Frequency = 1/ 40MHz = 25ns
 Instructions per second
Inst. per sec = 1/(CPI * Clock cycle time) = 6.67x10^{6} Inst./sec
 Suppose we have a program that has 268 instructions. How long will it take the program to run?
Program time = Inst. per program / (Inst. per sec) = 4.02x10^{5}s
Problem 4 (8 points)
 Draw a state diagram for a finite state machine that outputs 1 when it recognizes the pattern "01101001". For instance, if we have an input of "01101001101001" we should get an output of "00000001000001". (This means that for the last 8 bits whenever it sees the pattern it outputs 1)
 Modify the state diagram from the previous part such that it will only accept input sequences that start with "00" and still recognizes the pattern "01101001" from part a. For instance, given an input sequence "0001101001" we will get an output of "0000000001" and for the input sequence "1001101001" we will get an output of "0000000000"
Problem 5 (6 points)
Suppose we have a machine in which every instruction has the following format:
OPCODE 
DR 
SR1 
SR2 
Unused bits (if any) 
Where DR = Destination register, SR1 = Source Register 1, and SR2 = Source register 2.
 If the OPCODE section is 6 bits, how many opcodes can be represented?
We can represent 2^{n} values with n bits, so we are able to represent up to 64 opcodes
 If there are 64 registers, how many total bits are neede to represent DR, SR1, and SR2?
For each register field we will need ceil(log_{2}(# Registers)), so we get 6 bits * 3 fields = 18 bits total.
 If we have a 32bit instruction, 212 opcodes, and 168 registers, will we be able to represent all instructions? If so, how many bits will be unused? Give a reason for you answers.
For 212 opcodes we need ceil(log_{2}(# opcodes)) bits, so we get 8 bits for the OPCODE field. For 168 registers, we will need ceil(log_{2}(# Registers)) bits, so we get 8 bits for each register field. For the combination of OPCODE, DR, SR1, and SR2, we will need 8 + 3*8 = 32 bits, which leaves us with 0 unused bits.
Problem 6 (2 points)
Implement a gatelevel circuit using NOT, AND, and OR gates that will implement an odd parity check for a 3bit input. This means that when the input has an odd number of 1s, the output should be set to 0, and when the input has an even number of 1s, the output should be set to 1.
We should get the following truth table and corresponding circuit given an input ABC (A is the highest bit, C is the lowest) and the output Z
A 
B 
C 
Z 
0 
0 
0 
1 
0 
0 
1 
0 
0 
1 
0 
0 
0 
1 
1 
1 
1 
0 
0 
0 
1 
0 
1 
1 
1 
1 
0 
1 
1 
1 
1 
0 


