Computer Sciences Dept.

CS/ECE 252 Introduction to Computer Engineering

Fall 2011 Section 1
Instructor Guri Sohi
TAs Newsha Ardalani and Rebecca Lam

URL: http://www.cs.wisc.edu/~sohi/cs252/Fall2011/

Homework 5 // Due at lecture Mon, Oct 24

Primary contact for this homework: Rebecca Lam [rjlam@cs.wisc.edu]

You must do this homework in groups of two. Please write the full name and the student id of each member on every pages and staple multiple pages together. Only turn in ONE copy of homework per group.

Problem 1 (4 points)

Given the following LC-3 instruction

0110011001000010

answer the questions below. Assume PC = 0x00FF, R1 = 0xCAFE, R2 = 0xBA5E, R3 = 0x600F, and any accessed memory contains value 0x0000.
  1. What instruction type is it?
  2. What registers are used and how are they changed?
  3. What addresses are accessed, if any, and how are they changed?
  4. What is the next PC value?

Problem 2 (6 points)

Express the final value of R0 in terms of R1 and R2 after execution of the following LC-3 program. Show all work.

0x56E0
0x16E3
0x98BF
0x1921
0x1044
0x1004
0x16FF
0x03FB

Problem 3 (6 points)

A LD instruction is located at 0x3000.

  1. What is the largest address that this instruction can load from?
  2. If we suppose that the offset is a zero-extended unsigned number instead of a sign-extended 2's complement number, what is the largest address that this instruction can load from?
  3. If we hold the same assumption as part b, what is the smallest address this instruction could load from?

Problem 4 (4 points)

What, if any, changes would we have to make the following instructions if we increase the number of LC-3 registers to 32?

  1. AND (register mode)
  2. JMP
  3. STR
  4. BR

Problem 5 (6 points)

Suppose we have memory that has 512 locations and each location contains 8 bits.

  1. How many bits are required for the address?
  2. Suppose for Bass+Offset addressing mode we want to be able to access addresses 100 locations away from the base register. How many bits are required in the instruction to specify the signed offset?
  3. Suppose for PC-relative addressing mode we want to be able to access addresses 40 locations away. How many bits are required in the instruction to specify the PC-relative offset?

Problem 6 (4 points)

Write out the instructions (in hex) that will implement the specified task for each of the following parts. Give minimal solutions using the least number of instructions and registers.

  1. Store the 2's complement of R4 into R0 without overwriting R4
  2. Load the value at address 0x0003 into R1

 
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