CS/ECE 252 Introduction to Computer Engineering

Primary contact for this homework: Rebecca Lam [rjlam@cs.wisc.edu]

You must do this homework in groups of two. Please write the full name and the student id of each member on every pages and staple multiple pages together. Only turn in ONE copy of homework per group.

Problem 1 (4 points)

Given the following LC-3 instruction

0110011001000010

1. What instruction type is it?
   Load instruction
2. What registers are used and how are they changed?
   R1 and R3 are accessed. R1 is used as the base of the address to be accessed and R3 is loaded with the value at the address. R3 therefore = 0x0000 after the instruction is executed
3. What addresses are accessed, if any, and how are they changed?
   The address at value(R1)+offset6=0xCAFE + 0x2= 0xCB00 is loaded into R3. No changes at 0xCB00 are made
4. What is the next PC value?
   Since this is not a JMP or BR instruction, PC is incremented PC+1=0x0100

Problem 2 (6 points)

Express the final value of R0 in terms of R1 and R2 after execution of the following LC-3 program. Show all work.

0x56E0 R3 = R3 & 0x00
0x16E3 R3 = R3 + 3 -> R3 = 3
0x98BF R4 = NOT(R2)
0x1921 R4 = R4 + 1 -> R4 = -(R2), -R2+2 for final loop [START OF LOOP]
0x1044 R0 = R1 + R4 -> R0 = R1-R2+2 (final)
0x1004 R0 = R0 + R4 -> R0 = R0-R2+2 (final)
0x16FF R3 = R3 - 1
0x03FB branch if positive to start of loop, PCoffset=-5

Problem 3 (6 points)

A LD instruction is located at 0x3000.

1. What is the largest address that this instruction can load from?
   Using PC-relative mode, we can only access from PC-256 to PC+255. Since the PC is incremented as part of the FETCH phase, the largest address this instruction can load from will be at 0x3000 + 1 + 255 = 0x3100
2. If we suppose that the offset is a zero-extended unsigned number instead of a sign-extended 2's complement number, what is the largest address that this instruction can load from?
   We are given 9 bits, so for an unsigned number we can represent 0 to 2⁹-1. This means we can now access up to 0x3000 + 1 + 2⁹-1 = 0x3200
3. If we hold the same assumption as part b, what is the smallest address this instruction could load from?
   The lowest number we can represent is 0. This means the lowest address we can load from is 0x3000 + 1 = 0x3001

Problem 4 (4 points)

What, if any, changes would we have to make the following instructions if we increase the number of LC-3 registers to 32?

For 32 registers we will need log₂(32) = 5 bits. This is 2 more than originally.

1. AND (register mode)
   We have 3 registers for this so we need to add 2*3 = 6 bits total
2. JMP
   We have 1 register for this so we need to add 2 bits total
3. STR
   We have 2 registers for this so we need to add 2*2 bits = 4 bits total
4. BR
   No change

Problem 5 (6 points)

Suppose we have memory that has 512 locations and each location contains 8 bits.

1. How many bits are required for the address?
   ceil(log₂(512))=9 bits
2. Suppose for Bass+Offset addressing mode we want to be able to access addresses 100 locations away from the base register. How many bits are required in the instruction to specify the signed offset?
   In 2's complement we can represent -2^n-1 to 2^n-1-1, so 100=2^n-1-1 -> n=8 bits
3. Suppose for PC-relative addressing mode we want to be able to access addresses 40 locations away. How many bits are required in the instruction to specify the PC-relative offset?
   40=2^n-1-1 ->n=7 bits

Problem 6 (4 points)

Write out the instructions (in hex) that will implement the specified task for each of the following parts. Give minimal solutions using the least number of instructions and registers.

1. Store the 2's complement of R4 into R0 without overwriting R4
   R0 = NOT(R4) -> 0x913F
   R0 = R0+1 -> 0x1021
2. Load the value at 0x0003 into R1
   R1 = R1 & 0x00 -> 0x5260
   R1 = valueAt(value(R1)+3) -> 0x6243