Homework 5 [Due at lecture on Fri,Oct 26]
Primary contact for this homework: Junaid Khalid [junaid AT cs D0T wisc D0T edu ]
You must do this homework in groups of two. Please write the full name and the student id of each member on every page and staple multiple pages together.
Problem 1 (4 points)
Let's assume that PC = 0x0101, R1 =0x250F, R2=0xCAFE, R3 = 0xBEEF and any other accessed memory contains 0x0000
For the following LC-3 instruction
0001001010000001
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What type of instruction is it?
ADD instruction
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Which registers are used?
R1 and R2
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What is the value in R1, R2 and R3 after the execution of this instruction?
R1 = 0xF00D
R2 = 0xCAFE
R3 = 0xBEEF
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How are the n, p or z flags affected by the execution of this instruction?
n = 1
p = 0
z = 0
Problem 2 (6 points)
The following table shows a part of the LC-3's memory:
Address |
Content |
x3100 |
1001 001 001 111111 |
x3101 |
0101 010 010 000001 |
x3102 |
1001 010 010 111111 |
x3103 |
0000 010 111 111100 |
If the conditional branch redirects control to location x3100, state what is known about R1 and R2 before the execution of the program.
Branch is taken means that the result of the 3rd instruction; NOT(R2)=0, was zero. So, R2 was 0xFFFF at the end of the 2nd instruction. R1 AND R2 =0xFFFF implies that both R1 and R2 were 0xFFFF after the instruction 1. So at the start R1 was 0x0000 and R2 was 0xFFFF
Problem 3 (4 points)
How many times does the LC-3 make a read or write request to memory during the processing of following instructions?
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LD
2 ( one to fetch instruction + one to fetch data)
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LDR
2 ( one to fetch instruction + one to fetch data)
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LDI
3 ( one to fetch instruction + one to fetch address + one to fetch data)
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LEA
1 ( only to fetch instruction )
Problem 4 (6 points)
Assume we have a 256 bytes memory with 128 different addresses and 2 bytes are stored at each address
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How many bits are required for the memory addressing?
log2(128) = 7bits
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Assume we want to address 20 locations in both directions, how many bits are required for an instruction to specify the offset in Base+Offset addressing mode?
In 2's complement we can represent -2^(n-1) to 2^(n-1) -1
20 = 2^(n-1) -1
n = 6 bits
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Assume we want to address 20 locations in both directions, how many bits are required for an instruction to specify the offset in PC-relative offset addressing mode?
20 = 2^(n-1) - 1
n = 6 bits
Problem 5 (6 points)
Write out LC-3 instructions (in hex) for the implementing following tasks
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Subtract the value of R4 from R1 and store the result in R1
R4 = NOT (R4)
R4 = R4 + 1
R1 = R1 + R4
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Take the OR of R3 and R4 and store the result in R3
R3 = NOT(R3)
R4 = NOT(R4)
R3 = R3 AND R4
R3 = NOT(R3)
Problem 6 (3 points)
We would like to have an instruction that does nothing. Many ISAs actually have an opcode devoted to doing nothing. It is usually called NOP, for NO OPERATION. The instruction is fetched, decoded and executed. The execution phase is to do nothing! Which of the following three instructions could be used for NOP and have the program still work correctly?
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0001 001 001 1 00000
ADD R1, R1, #0 differs from a NOP because it sets modifies the flags
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0000 111 000 0 00001
BRnzp #1, Unconditionally branch to one after the next address in the PC. Therefore this instruction is not the same as NOP
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0000 000 000 0 00000
Same as NOP
Problem 7 (3 points)
If the condition codes have values N=0, Z=0, P=1 at the beginning of the execution of the following sequence of instructions, what will their values be at the end of the execution of the following sequence of LC-3 instructions?
x3050 0000 0010 0000 0010 -> BRp #2
x3051 0101 0000 0010 0000 -> does not execute
x3052 0000 1110 0000 0010 -> does not execute
x3053 0101 0000 0010 0000 -> R0 = R0 AND #0
x3054 0001 0000 0011 1111 -> R0 = R0 ADD #-1 -> R0 = -1
N=1, Z=0, P=0
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