CS/ECE 252 Introduction to Computer Engineering

Problem 1 (2 points)

Assume a memory's addressability is 64 bits. What does that tell you about the size of the MAR and MDR?

The addressability of a memory is the number of bits in each location. So if a memory's addressability is 64 bits, then each location is 64 bits long. The MDR has the same size as the memory locations, so the MDR is 64 bits long.

The size of the MAR is determined by the number of locations, which is not mentioned here, so we cannot determine the size of the MAR.

Problem 2 (2 points)

List four LC-3 operations that cause the condition codes to change.

ADD, AND, NOT, LD, LDI, LDR, and LEA.

Problem 3 (3 points)

Say we have a memory consisting of 256 locations, and each location contains 16 bits.

1. How many bits are required for the address?
   
   We need to be able to uniquely represent each memory location, so we require log_2(256) = 8 bits.
   
   
2. If we use the PC-relative addressing mode, and want to allow control transfer between instructions 30 locations away, how many bits of a branch instruction are needed to specify the PC-relative offset?
   
   We need at least 6 bits, since PC-offsets are in 2's complement representation. This would allow the address to be within +32 or -31 locations of the LD or ST instruction since the PC is incremented before the offset is added.
   
   
3. If a control instruction is in location 5, what is the PC-relative offset of address 15? Assume that the control transfer instructions work the same way as in the LC-3.
   
   The incremented PC is 6. This means that the PC-relative offset of address 15 is 15-6=9.

Problem 4 (3 points)

Write LC-3 instructions in hex for implementing the following tasks.

1. Using a single instruction, move the value of R1 into R3.
   
   0101 011 001 1 11111 = 0x567F; AND R3, R1, #FF
   or
   0001 011 001 1 00000 = 0x1660; ADD R3, R1, #0
   
   
2. Using a single instruction, clear the contents of R2.
   
   0101 010 010 1 00000 = 0x54A0
   
   
3. Using multiple instructions, perform the operation R1 minus R2 and store the result in R3.
   
   1001 010 010 111111 = 0x94BF; NOT R2
   0001 011 010 1 00001 = 0x5793; ADD R3, R2, #1
   0001 011 001 0 00 011 = 0x5699; ADD R3, R1, R3
   
   

Problem 5 (2 points)

What is the largest positive number we can represent literally (i.e., as an immediate value) within an LC-3 ADD instruction?

The imm5 field is in 2's complement representation and has 5 bits, so the largest number we can represent is 2^(n-1) - 1 = 2^4 - 1 = 15.

Problem 6 (4 points)

Consider the LC-3 program below.

Address	Instruction
x4000	1001 010 001 111111
x4001	0001 010 010 1 00010
x4002	0101 011 010 0 00 011
x4003	0000 0 1 1 000000110

1. Assume that the PC is initially set to x4000 and that the initial contents of the registers R1, R2, and R3 are the values in the table below. Fill out the table for the values of R1, R2, R3, and the PC after the line 0x4003 is executed.
   
   

   	Initial	After x4003
   R1	1	1
   R2	2	0
   R3	3	0
   PC	x4000	x400A

   
   
   Which condition codes are set? Z
   
   
2. Now assume that the PC is again set to x4000 and the initial contents of the registers R1, R2, and R3 are the values in the next table. Fill out the same missing information.
   
   

   	Initial	After x4003
   R1	2	2
   R2	-1	-1
   R3	-1	-1
   PC	x4000	x4004

   
   
   Which condition codes are set? N
   

Problem 7 (2 points)

We are about to execute the following code snippet. Assume that before execution R1 = 0x4023 and that the value stored at 0x4010 is 0x4015. Complete each of the below LC-3 machine instructions so that each instruction loads the data at address 0x4015 into R3, or indicate that it is not possible and why.

Address	Instruction
x4000	0010 011 000010100
x4001	1010 011 000001110
x4002	0110 011 001 110010
x4003	1110 Cannot be done since the LEA instruction loads an address into R1, not the value at the address.

Problem 8 (2 points)

The LC-3 does not have an opcode for logical function NOR. That is, there is no instruction in the LC-3 ISA that performs the NOR operation. However, we can write a sequence of instructions to implement the NOR operation. The three instruction sequence below performs the NOR of the contents of R0 and R1 and puts the result in R2. Fill in the two missing instructions so that the three instruction sequence will do the NOR operation.

1) 1001 011 000 111111
2) 1001 100 001 111111
3) 0101 010 011 0 00 100

Problem 9 (10 points)

We are about to execute the program below. Assume the condition codes before execution are N=1, Z=0, P=0.

Address	Instruction	Comment
x3000	0101 001 001 1 00000	R1<-R1 AND 0
x3001	0001 001 001 1 00010	R1<-R1 + 2
x3002	0010 010 011111101	R2<-Mem[0x3100]
x3003	0000 0 0 1 000000011	Branch if P to 0x3007
x3004	0011 001 011111101	Mem[0x3102]<-R1
x3005	0000 0 1 0 000000001	Branch if 0 to 0x3007
x3006	0011 001 011111100	Mem[0x3103]<-R1
x3007	1111 0000 00100101	HALT

1. Fill in the comments for the above program describing what each instruction does. For example, if one of the instructions was 1001 0100 1111 1111, then the comment for this instruction can be either "This instruction stores the complement of value at R3 into R2" or "R2 <-- NOT(R3)".
   
   
2. If the initial condition of the memory locations 0x3100 to 0x3103 before executing the code are as shown below (i.e., all are 0), what are the final values at these memory locations after executing the code?
   
   

   Address	Initial Value	Final Value
   x3100	x0000	0x0000
   x3101	x0000	0x0000
   x3102	x0000	0x0002
   x3103	x0000	0x0000

   
   
   
3. If the initial conditions were different (i.e., value at 0x3100 is now changed to 0xFFFF, as shown in the table below) and then the program is run, what would be the final value at the memory locations 0x3100 to 0x3103 after executing the code?
   
   

   Address	Initial Value	Final Value
   x3100	xFFFF	0xFFFF
   x3101	x0000	0x0000
   x3102	x0000	0x0002
   x3103	x0000	0x0002

   
   
   
4. If the whole memory is shifted up by 0x1000, i.e., if the instructions start at 0x2000 (instead of 0x3000) and the data values start at 0x2100 (instead of 0x3100), will these instructions still work? Specify why or why not.
   
   Yes, because this code relies on PC-relative addressing for all memory-related instructions (i.e., loads and stores) and branch instructions.