# CS/ECE 252 Introduction to Computer Engineering

Spring 2013 Section 1 & 2
Instructors Mark D. Hill and Guri Sohi
TAs Preeti Agarwal, Mona Jalal, Rebecca Lam, Pradip Vallathol

URLs: http://www.cs.wisc.edu/~markhill/cs252/Spring2013/ and http://www.cs.wisc.edu/~sohi/cs252/Spring2013/

## Homework 5 [Due at lecture on Mon, Mar 18]

Primary contact for this homework: Rebecca Lam [rjlam@cs.wisc.edu]

You should work in groups of two for this homework. Please write the full name (as it appears on Learn@UW) and the student ID of each group member on every page and staple multiple pages together.

### Problem 1 (2 points)

Suppose we increase the number of registers in the LC-3 to 64 and keep the instruction size at 16 bits. Will this cause any problems with the ADD (non-immediate) instruction? Explain.

Yes, 6 bits are needed to specify 64 registers meaning each register field needs 3 more bits each (9 more bits total). Even with the 2 unused bits we will not have enough bits in the ADD instruction to specify 64 registers for each operand.

### Problem 2 (2 points)

1. (1 point) Write a single LC-3 instruction in hex to move the value of R2 into R3.

0001 011 010 1 00000 = 0x16A0 ;ADD R3, R2, #0
or
0101 011 010 1 11111 = 0x56BF ;AND R3, R2, #FF

2. (1 point) Write a single LC-3 instruction in hex for clearing (zeroing) the contents of R1.

0101 001 001 1 00000 = 0x5260 ;AND R1, R1, #0

### Problem 3 (4 points)

Suppose that we have a memory consisting of 128 locations and each location contains 32 bits.

1. (2 points) How many bits are required for the address?

ceil[ log2(128)] = 7 bits

2. (2 points) If we use the PC-relative addressing mode and want to allow control transfer to instructions 10 locations away (in either direction), how many bits of a branch instruction are needed to specify the PC-relative offset?

ceil[ log2(10 + 1) + 1] => 5 bits

### Problem 4 (4 points)

We are about to execute the following code snippet. Assume that before execution R0 = 0x3030 and that the value stored at 0x300A is 0x3020. Complete each of the below LC-3 machine instructions so that each instruction loads the data at address 0x3020 into R1, or indicate that it is not possible and why.

0x30000010 001 000011111 = 0x221F
0x30011010 001 000001000 = 0xA208
0x30020110 001 000 110000 = 0x6230
0x3003

Cannot be done since the LEA instruction loads an address into R1, not the value at the address.

### Problem 5 (4 points)

Write the LC-3 machine instructions in hex that will implement the following. Give a solution that is 1-2 instructions long and uses a minimal number of registers.

1. (2 points) Suppose PC = 0x3000 and R0 = 0x5000. Store the 1's complement of the value at memory address 0x5004 into R1 without overwriting R0.

0110 001 000 000100 = 0x6204 ;LDR R1, R0, 4
1001 001 001 111111 = 0x927F ;NOT R1, R1

2. (2 points) Assume PC = 0x4000 and the value at memory address 0x400A is 0x8000. Store the most significant bit of R2 into R0.

0010 000 000001001 = 0x2009 ;LD R0, 0x400A
0101 000 000 000 010 = 0x5002 ;AND R0, R0, R2

or

0010 000 000001001 = 0x2009 ;LD R0, 0x400A
0101 000 010 000 000 = 0x5080 ;AND R0, R2, R0

### Problem 6 (3 points)

What are the values of R0 in terms of R1 and R2 (e.g. R0 = R1 * R2) after execution of the following code snippet? Show all work by translating each instruction. The first instruction has been translated for you. Note: #0 is the value 0, not register 0.

```0101 0000 0010 0000	;ADD R0, R0, #0		R0 = 0
0101 0110 1110 0000	;AND R3, R3, #0		R3 = 0
0001 0110 1110 0011	;ADD R3, R3, 3 		R3 = 3
0001 0010 0100 0001	;ADD R1, R1, R1		R1 = 2*R1' (loop start)
0001 0000 0000 0010	;ADD R0, R0, R2		R0 = R0' + R2
0001 0110 1111 1111	;ADD R3, R3, -1		R3 = R3'-1
0000 0011 1111 1100	;BRp (PCoffset=-4)	if R3<0 branch to loop start (executes 3 times)
0101 0000 0000 0001	;R0 = R0' AND R1
```

R0 = (R1 * 23) AND (R2*3)

### Problem 7 (5 points)

We are about to execute the program below. Assume the condition codes before execution are N=0, Z=0, P=1.

0x30000011 0000 0000 1011ST R0, 0x300C
0x30010000 0010 0000 0011BRp 0x3005
0x30021001 0000 0011 1111NOT R0, R0
0x30030001 0000 0010 0001ADD R0, R0, #1
0x30041111 0000 0010 0101HALT
0x30051010 0010 0000 0111LDI R1, 0x300D
0x30061111 0000 0010 0101HALT

Suppose a section in memory before execution of the program is as follows:

0x300A0xABCD
0x300B0xFEED
0x300C0xBEEF
0x300D0x300C
0x300E0x300A
0x300F0xBABE

Given the initial values of the below registers, fill in the values after the program has completed execution (reached a HALT). Give your answers in hex.

RegisterInitial ValueFinal Value
MAR0x300E0x300C
R00x00000x0000
R10x43210x0000
R20x12340x1234

### Problem 8 (2 points)

If R0=0 and the condition codes have the values N=0, Z=0, P=1 before execution of the following three instructions, what are the values of R0 and the condition codes after execution of the instructions?

```x3050	0000 0010 0000 0001	;BRp PCoffset=1
x3051	0101 0000 0010 0000	;skipped
x3052	0001 0000 0010 0001	;ADD R0, R0, #1
```

R0=1, N=0, Z=0, P=1

### Problem 9 (2 points)

The following LC-3 branch instruction is located at memory address 0x5F55:

0000 1011 0000 0000

If the branch is taken, what does that imply about the values of the condition codes before the instruction executed?

It means either N of P flags were set and that Z = 0

### Problem 10 (2 points)

List four LC-3 operations that do not cause the condition codes to change.

BR, JMP, JSR, JSRR, RET, RTI, ST, STI, STR, TRAP

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