Table of Contents

What's New:  look here for updates	Lecture
Course Mailing List Archive	Homeworks
Course Schedule	Project
Course Description	Examinations
Instructor	Incompletes and Academic Misconduct
Teaching Assistant	Grading
Required Course Material	Miscellanea
Handouts	Verilog/VHDL Links
Course Reference Material	Force File Links

 What's New

• (4/29/2005) Homework 5 solution, final exam syllabus, sample final exam posted.
• (4/27/2005) Homework 4 solution posted.
• (4/13/2005) Homework 5 posted.
• (3/31/2005) Project assembler and test files posted.
• (3/30/2005) ECC handout, midterm solution and homework 4 posted.
• (3/10/2005) Schedule update - no class on Monday, March 14.
• (3/4/2005) Schedule update - no class today.
• (3/3/2005) Homework 3 solution posted.
• (2/22/2005) Midterm syllabus posted.
• (2/22/2005) Homework 2 solution posted.
• (2/16/2005) Homework 3 posted.
• (2/16/2005) Verilog notes posted.
• (2/2/2005) Homework 2 posted.
• (2/2/2005) Verilog links posted.
• (1/19/2005) Homework 1 posted.
• (1/12/2005) Class web page posted.

 Course Mailing List Archive

 Course Schedule

 Course Description

CS/ECE 552 serves students in two ways. First, for those who will continue in computer architecture, it lays the foundation of detailed implementation experience necessary to make the quantitative tradeoffs found in CS/ECE 752 and 757 meaningful. Second, for those students not continuing in computer architecture, it unifies concepts introduced in CS/ECE 352 and 354 and solidifies an intuition about why hardware is as it is.

CS/ECE 552 assumes that you are familiar with the material in the prerequisites CS/ECE 352 and 354, especially:

• Knowledge of a high-level language
• Understanding of computer data structures
• Knowledge of stack mechanisms and procedure calls
• Understanding of assembly language programming: opcodes, operands, etc.
• Boolean logic design techniques
• Realization of boolean functions using AND, OR, NOT, XOR, NAND, NOR gates and appropriate minimization techniques
• Logic building blocks: flip-flops, multiplexers, decoders, shift registers

 Instructor: Guri Sohi

Office:         6375 Comp Sci & Stat
Phone:          262-7985
Email:          sohi@cs.wisc.edu
Office hours:   MW 2:30pm - 3:30pm

 Teaching Assistant: Dave Mulvihill

Office:         1301 Comp Sci & Stat            
Phone:          262-6600
Email:          mulvihil@cs.wisc.edu
Office hours:   Tuesday/Thursday 2:30-4pm, Friday 10:30-11:30am and by appointment

 Required Course Material

Note:  The web page about the course textbook has a lot of interesting information.  Be sure to look through it early in the semester.

 Handouts

• Getting Started with Mentor READ THIS THOROUGHLY
• Sharing Files in your Mentor Directory
• Mentor overview from a previous semester. Covers some basic ideas.
• Various Mentor documentation in postscript. Potentially helpful, but not guaranteed to be up to date. (NOTE -- this may be the same as the mgcdocs help information.)
• Yet another Mentor overview from Santa Clara University.

 Course Reference Material

• Peter J. Ashenden, The Designer's Guide to VHDL - On reserve at Wendt library
• J. P. Hayes, Computer Architecture and Organization
• Rafiquzzaman and Chandra, Modern Computer Architecture
• J. Wakerly, Digital Design Principles and Practices
• V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization
• Search the UW Libraries

 Lecture

Time:           1:00 pm - 2:15 pm Monday, Wednesday and Friday
Place:          103 Psychology

Prof. Mark Hill's Lecture Notes: (These serve as a useful reference; Univ. of Wisconsin-Madison only)

• Chapter 1: Introduction
• Chapter 2: Performance
• Chapter 3: Instructions
• Chapter 4 Part I: Basic Arithmetic
• Chapter 5 Part I: Datapath
• Chapter 5 Part II: Control
• Chapter 5 Part III: Microprogramming & Exceptions
• Chapter 6: Pipelining
• Chapter 7 Part I: Caches
• Chapter 7 Part II: Memory and Virtual Memory
• Chapter 4 Part II: More Arithmetic
• Chapter 8 I/O
• Chapter 9 Parallel Processing
• ECC Handouts
• Verilog lecture notes

 Homework

• Homework 0
• Homework 1
  Solution
• Homework 2
  Solution
• Homework 3
  Solution
• Homework 4
  Solution
• Homework 5
  Solution

The first three assignments (and the project) will require the use of the Mentor Graphics design automation tools. Students will have accounts to run the Mentor tools in CS, on linux workstations. These workstations are in rooms 1350, 1358, 1366, and l368 in CS. We do not support the running of Mentor on any other machines. In case you  want to use X-terminal to work remotely, see the document runningMentorRemotely for information about how to do this.

Students new to Unix should attend to CSL orientation session during the first two weeks of class (see posters in CS building) and consult the CS 1000 handout.

For information about homework assignments, see the course schedule.

 Project

• ISA Specification for Spring 2005
• Memory Specification
• Project FAQ


• VHDL Files used in the project:
• cache.vhdl
• mem.vhdl
• sample_input.in
• An example on how to use the VHDL memory unit


• Grading Policy
• Hints for Pipelining

WISC-SP05 Assembler

• asmsp05 def.h hex2dec
• Directions for the use of the assembler

Test Programs

• t1.asm            t1.mem            t1.dm_cache
• t2.asm            t2.mem            t2.dm_cache
• t3.asm            t3.mem            t3.dm_cache
• t4.asm            t4.mem            t4.dm_cache
• t5.asm            t5.mem            t5.dm_cache
• t6.asm            t6.mem            t6.dm_cache

The files demo.force and demo_cache.force are the force files from a former project demo.   Look at them and make your own force file for the project demo following these examples. Note: in these file the I$205 is the handle particular to this block. Don't just copy them, they won't work as is for your design. It is a good idea to trace the same sort of signals included in these force files. You may add other signals if you find them necessary.

 Examinations

Midterm solution

Midterm syllabus: pdf ps

Previous midterms:
Spring 1999
Spring 2003 Solution
Fall 2003 Solution

Final exam syllabus: pdf ps

Previous final exam:
Spring '92, Solution

 Incompletes and Academic Misconduct

 Grading

• 20% Homework
• 20% Project
• 30% Exam 1
• 30% Exam 2

 Miscellanea

• Mentor Tutorial
• CSL Frequently-Asked Questions (FAQs)
• University of Wisconsin CS Computer Architecture Group
• World-Wide Computer Architecture Information
• Running mentor remotely from a windows PC.

 Verilog/VHDL Links

• Compiling and Simulating Verilog at CS
• Compiling and Simulating VHDL at CS

• Verilog HDL On-line Quick Reference
• Another Verilog manual

• VHDL Guide from Purdue ASIC design class
Detector 101,  source code and state diagram
• VHDL tutorial
• Lots of VHDL examples from The Designer's Guide to VHDL by Peter Ashenden.  If you want even more information, you may want to look at The Student's Guide to VHDL by the same author. (About $30 from Amazon.com.)
• A VHDL tutorial
• VHDL file for 2 bit counter
• VHDL file for state machine
• VHDL file for 5-1 16-bit mux

 Force File Links

•  Sample force file for Quicksim II/Qhpro
•  Sample force file for Qhsim
•  Sample force file for the 2 bit counter listed in the VHDL links.