CS/ECE 552-1: Introduction to Computer Architecture
Spring 2005
Problem Set #1
Due: Wednesday,February 2nd, 2005
Approximate Weight: 20% of the Homework Grade
You should do this assignment by yourself.

The main objective of this problem set is to become familiar with the Mentor CAD tools and the Sun workstations. The " Getting Started with Mentor" handout is available on the CS552-1 Web page. Please go through the handout carefully and completely. Additional Mentor documentation is available on-line as part of the Mentor help system and in the directory ~cs552-1/public/UsefulFiles/. Try to learn as much as possible about the use of Mentor tools (Design Architect, Design Manager, mgc_acro , and Quicksim II) because you will be using them throughout the semester.

You should simulate your solutions using QuickSim II to both verify the correct function of your designs for yourself and to hand in to me so that I can see that your solutions work. You also have to hand in printouts of the logical layout of your designs (the schematic files) and their external interfaces (a printout of the symbolic version).

This assignment will take a significant amount of time if you are not already familiar with the Mentor CAD tools. Get started as soon as possible.

To deal with circuit complexity, a "divide and conquer" approach is used. For design, the circuit is broken up into pieces called blocks. These blocks are interconnected to form the circuit. This design approach is referred to as hierarchical design. A hierarchy also reduces the complexity required to represent the schematic of a circuit. You will use this technique in problem 1 and problem 3.

Problem 1 25 points

The objective of this problem is to design a 4-bit comparator hierarchically. You are allowed to use only inverters and 2-input NAND gates.

a) Design a 1-bit comparator using only inverters and 2-input NAND gates. This comparator has 2 1-bit inputs. Its output is 1 if and only if both inputs are the same. Implement the circuit in Mentor Design Architect. Create a symbol for the 1-bit comparator. NOTE: The input data lines of the comparator should be labeled starting with I(1:0) (eg I₁, I₀) and the output with OUT.

b) Use QuickSim II to exercise the symbolic version of your 1-bit comparator over all possible combinations of inputs.

b) Use the symbol of the 1-bit comparator you designed in part (a) to hierarchically create a 2-bit comparator. Create a symbol for your 2-bit comparator.

c) Hierarchically create a 4-bit comparator using the symbolic version of your 2-bit comparator. The inputs to the new comparator should be 4-bit buses (NOT single wires) labeled "A(3:0)" and "B(3:0)", and the output should be a single wire labeled "OUT". Test the comparator you created using QuickSim II and print out annotated results of your simulations.

d) Turn in printouts of both the gate level schematics and top-level symbols.

Problem 2 20 points

a) Design a 3-to-8 decoder, again using only inverters and basic 2-input AND and OR gates. Implement the circuit in Mentor Design Architect. The circuit should have inputs labeled I(2:0) i.e. I₂ through I₀ and outputs labeled OUT(7:0) i.e. OUT₇ through OUT₀. Create a symbol for your decoder.

Turn in printouts of both the gate level schematic and the top level symbol.

b) Use QuickSim II to exercise the symbolic version of your 3-to-8 decoder over all possible combinations of inputs. Print the resulting trace and label each set of inputs and the corresponding outputs and discuss whether or not the operation of the gate is correct.

Problem 3 20 points

The objective of this problem is to design an 8-to-1 multiplexor (mux) hierarchically.

a) Design a 2-to-1 mux using AND, OR and NOT gates. Implement the circuit in Mentor Design Architect. Create a symbol for the 2-to-1 mux. NOTE: The input data lines of the mux should be labeled starting with I(1:0), the select line should be S and the output line with OUT.

b) Use QuickSim II to exercise the symbolic version of your 2-to-1 mux over all possible combinations of inputs.

b) Use the symbol of the 2-to-1 mux you designed in part (a) to hierarchically create a 4-to-1 mux. Create a symbol for your 4-to-1 mux. NOTE: Make your select-bus (not single wires) S(1:0) i.e. S₁ and S₀

c) Hierarchically create an 8-to-1 mux using the symbolic version of your 4-to-1 mux. The inputs to the new mux should be 8-bit bus (NOT single wires) labeled "I(7:0)" , the select-bus labeled S(2:0) and the output should be a single wire labeled "OUT".

d) Test the mux you created using QuickSim II and print out annotated results of your simulations.

e) Turn in printouts of both the gate level schematics and top-level symbols.

Problem 4 35 points

A sequence detector is a finite state machine that outputs "1" when a particular sequence is detected and outputs "0" otherwise. For example, a sequence detector designed to detect the sequence "1010" outputs "1" every time this sequence is seen in the input stream. Thus, for an input stream "101010" the output will be "000101".

Design a sequence detector that detects the sequence that corresponds to the last two digits in your ID number, represented in binary coded decimal(BCD). For example, if your id is 902 631 9385 , the last two digits being 85, the sequence detector will detect 85, which is 10000101 in BCD.

You should complete each of the following:

Construct the state diagram of the machine. Turn in the state diagram.
Implement the sequence detector using Design Architect. Create a symbol for your detector. Turn in printouts of both the circuit level and symbolic versions of your detector.
Simulate your design using QuickSim II. You should chose an input sequence that shows that your detector works correctly. Be sure to turn in the annotated trace of your simulation and describe why the sequence shows that your detector works properly.
Please make a note of your ID number.