CS/ECE 552-1: Introduction to Computer Architecture
Spring 2005
Problem Set #2

Due: Wednesday, February 16, 2005
Approximate Weight: 20% of the Homework Grade
You should do this assignment in groups of two.


Problem 1: 25 points

Design an 8 -by -16- bit register file using the Mentor Graphics software. Figure 1 gives the high-level interface.  It has one write port, two read ports, three register select inputs (two for read and one for write,) a write enable, a read enable, a reset and a clock input.


Figure 1:  The device for problem 1.

The read and write ports are 16 bits each. The select inputs (read and write) are 3 bits each. The read or write enable must be asserted (high) for the corresponding operation to take place. The read enable selects the read ports, i.e. when the read enable is asserted, the data from the selected registers will be driven on to the corresponding  read ports. When the read is disabled (i.e. read enable is low) the read ports must be in tri-state (high impedance state).

The write enable signal selects the write port.  The write must be performed in the first half of the clock cycle (rising edge of the clock) so that the value may be read in the second half of the clock cycle.

The reset signal is synchronous and when asserted (active high), resets all the register values to 0.

You should use a hierarchical design. It is a good idea to design a 16-bit register first and then put 8 of them together with additional logic to build the register file. For simulation purposes, any signal that is wider than one bit should be represented as a bus going into or out of your system. For a 16-bit bus, there should not be 16 signals on your trace output.

Hand in printouts of schematic sheets for all of your building blocks along with your annotated simulation traces. The simulation trace must show that every register can be read and written. You should also include a case of simultaneous read and write on the same register and a case of read and write at the same cycle but on different registers.

Problem 2: 25 points

Design a simple 16-bit ALU using Mentor. Operations to be performed are ADD, bitwise-AND, bitwise-OR, and bitwise-XOR.  In addition, it must have the ability to invert the B input before performing the operation. Use a carry look-ahead adder (CLA) in your design.  (Hint: First design a 4-bit CLA. Then use blocks of this CLA for designing the 16-bit CLA.)
 
 
OP code
 Function Result
00 ADD A + B
01 OR A OR B
10 AND A AND B
11 XOR A XOR B
 Table 1:  OP code definitions.
The external interface of the ALU should be: In case of logic functions, OFL is not asserted (ie. kept logic low).

For an ADD operation, you can assume that the operands and results are in 2's complement form for the purposes of overflow detection.

Use hierarchical design and simulate each block by itself before you try the complete design.

You should hand in:

  1. Schematic sheets of all the blocks that you designed.
  2. Annotated simulation trace output of the complete design.  Pick representative cases for your simulation input.
  3. Perform subtraction using your ALU and turn in annotated trace results showing that it operates correctly.  You should subtract the following:
    1. 546 - 35
    2. -214 - 214
    3. -214 - (214 + 1)
    4. 1 - (-215).  Note:  This means set A=1 and B="the 2's complement representation for the number -215."
  4. Perform arithmetic using your ALU and turn in annotated trace results showing that it operates correctly. You should perform the following arithmetic:
    1. 26 - 25
    2. 25 - 26
    3. 16384 - 0
    4. 1 + (215 - 1)

Problem 3: 15 points

Problem 4: 15 points

Problem 4: 10 points

Problem 6: 5 points

Problem 7: 5 points