CS/ECE 552-1: Introduction to Computer Architecture
Spring 2005
Problem Set #4
Due: Wednesday, April 13
Approximate Weight: 20% of the Homework Grade
You should do this assignment alone --
NOT with your
project partner.
Problem 1 (25 points) cache mapping strategy
Problem 7.7 on page 628 of the textbook. Problem 7.20,
7.22 on page 630 of the textbook.
Problem 2 (10 points) cache of unusual size
Problem 7.25 on page 631 of the textbook. The qualification of whether or not a cache with 3K words is possible is if the normal addressing scheme for that cache (direct-mapped, set-associative, or fully-associative) works correctly.
Problem 3 (15 points) Associativity & replacement policy vs. performance
Problem 7.23 on page 630 of the textbook. Please add
an explanation as to why your answer is correct. An answer without explanation
will NOT receive any credit.
Problem 4 (20 points) cache performance analysis
Exercise 7.27 on page 631 of the textbook.
Problem 5 (15 points) virtual memory page tables
Exercise 7.32 on page 632 of the textbook.
Problem 6 (15 points)
Design an 8MB memory that is 128b wide, using 512K x 8b static RAMs. Please
make your figure neat and legible. Otherwise, you may lose points even
if your design happens to be correct.
Note: A generally accepted notation is B for byte, b for bit,
MB for megabyte, and Mb for megabit.
-
Give a block diagram of the design. Describe the external interface
of the 512K x 8b chip that you are using.
-
Suppose the memory must be both byte and word addressable, with the mode
of access specified by an extra control line called size.
You will need four more address bits to specify a byte address. Modify
your design to include byte addressability.