HINTS FOR PIPELINING

After you have the multi-cycle datapath working, you can easily convert it to a high-CPI pipelined datapath by inserting latches to create the pipeline stages and setting up the control so that only one instruction is in the pipeline at a time.

For a pipeline of length 5, the CPI is now 5.  There is no possibility of hazards.

You can then modify the pipeline control so that you move closer and closer to the optimal CPI of 1.  In some cases, hazards will be introduced.  They must be detected and pipeline bubbles must be introduced to eliminate them.  Each hazard will increase the average CPI for a given program.  Being over-careful (the original pipeline with a CPI of 5 is the extreme case of this) will result in a higher average CPI for a given program.

You can measure the CPI of your pipeline by modifying the memory system VHDL code so that it always has a latency of zero.  Then the CPI of the pipeline is the total number of cycles to execute a program, divided by the number of instructions executed.  (You can subtract the few cycles that are wasted as the pipeline fills/empties to get an exact value.)

Do not worry too much about getting the lowest possible CPI.  It is most important to make sure that the pipeline executes correctly.  You can then start to add optimizations to lower the CPI.  I do not know what is a reasonably low CPI.  I will find that out by comparing the results from each group.  My guess is that an average CPI between 2 and 3 will be pretty good for programs which are not optimized to produce a low CPI.  (Remember, changing the order of instructions can change the CPI for a program.)

MEMORY NOTE:  All versions of the memory unit should look the same to both datapaths.  The memory can be thought of as a box to which write and read requests are sent.  Both datapaths stall until the memory system responds.  All three versions of the memory system look the same, except for the latencies that they deliver.

Keep in mind that the memory system affects IPC, but not CPI.