CS/ECE 552-1: Introduction to Computer Architecture
Spring 2005
Term Project: WISC-SP05 Architecture
Grading Specification
Goal
The first goal of the project is to get the full instruction
set implemented and working. The "base" project is an implementation
of the instruction set with no cache memory. There are two ways to
improve your design, the first is to optimize your CPU and the second is
implement a cache memory structure. The more you do of each, the
better your grade will be. Here is a list of the general grading
expectations:
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5%: The progress report.
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65%: The multi-cycle (non-pipelined)
version of the datapath.
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5%: The no-cache memory system.
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5%: The direct-mapped cache memory system.
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20%: The final report.
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2% extra credit: The set-associative cache memory system. This
is only valid with everything above this point working correctly.
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10% extra credit: The pipelined version of the datapath. This
is only valid with everything above this point working correctly.
Final Report
The report is formal in the sense that it should be typed,
well written, and well organized. A sloppy, poorly written, or error-filled
(semantic, spelling, gramatical errors, etc.) report will be penalized.
You need to include the following items in your report:
Note: Please clearly label each
report section with the number presented below. Please include them
IN ORDER when you turn in your final report.
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A brief overview of your design.
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A discussion of how you optimized your CPU (this includes
the datapath and the control.)
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A table showing the number of clock cycles needed for each
instruction. This data is based on the state diagram of your multi-cycle
datapath control.
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A discussion of what does not work or what you would have
liked to have done. For each part of the implementation that does
not work, turn in a trace that demonstrates what the problem is and a discussion
of how you found the problem and how you would go about fixing it.
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A section outlining what you learned by doing this project.
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Schematics or VHDL source (using VHDL for Memory Controller
is optional, if you're familiar with it then use it) for all parts you
have not already turned in for homeworks.
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Printouts of test assembly code that you wrote to test your
design. These printouts should include comments about what is tested
by each section of code.
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A state diagram for each control module in your design.
This will include the memory system and datapath controllers and any other
state machine control module in your design.
All printouts should be well annotated,
especially
simulation results.
Deadlines
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Progress Report - Due April 6 (5% of project grade)
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Each group needs to turn in a typed report (1 page single-spaced
max) discussing how things are going. In addition, you need to turn
in the state diagrams of your CPU controller and your memory controller
along with a printout of the top level datapath for the entire design.
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Demonstrations - May 3-4
(75% of project grade)
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You and your partner will demonstrate that your design works.
We will provide you most of the test programs that will be used in the demonstrations.
Be prepared to answer questions related to your design. Both partners
are required to be present.
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Final Report - Due May 4 (20% of project grade)